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TDA8753A Folha de dados(PDF) 5 Page - NXP Semiconductors |
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TDA8753A Folha de dados(HTML) 5 Page - NXP Semiconductors |
5 / 20 page 1996 Jan 12 5 Philips Semiconductors Product specification YUV 8-bit analog-to-digital interface TDA8753A FUNCTIONAL DESCRIPTION Analog-to-digital converter The TDA8753 implements 3 independent CMOS 8-bit analog-to-digital converters. The converters use a multi-step approach with offset compensated comparators. Clamping An internal clamping circuit is provided in each of the 3 analog channels. The analog pins INY, INV and INU are switched to on-chip clamping levels during an active pulse on the clamp input CLP.The clamping level in the Y channel is code level 16. The clamping level in the U/V channel is code level 128 (output code 0 in the 2's complement description) see Tables 3 and 4. Sample rate converter A sample rate converter is integrated in the TDA8753A to facilitate programming of the horizontal aspect ratio which can be varied from a factor 1 to 2. This includes conversion from 16/9 to 14/9 and 4/3. In the U/V channel a linear interpolation is sufficient because of the four times oversampling. Discrete time oscillator (DTO) A discrete time oscillator is used to calculate for every sample of the phase delay that is needed for a given compression factor. Serial interface (SIO) All controls are sent to the TDA8753A via a serial microprocessor interface. Data from this interface will be made active at the vertical input pulse V50. The TDA8753A has three addressable control registers which can be loaded via the signals UPDA and UPCL. The format of this bus is fixed according to mode 0 of the 8051 family UART at 1 Mbaud (8 bits are transmitted, LSB first). Serial interface protocol POWER-ON STATE When powered up the SIO is in an unknown state and all data in the registers is random. When signals are applied to UPCL and UPDA in this state, the behaviour is unpredictable. The only way to exit from this state to a known state is apply a V50 signal to the TDA8753A. INITIALIZATION STATE From power-on or any other state, the INIT state is entered (at the latest) one TDA8753A clock period after the end of the V50 HIGH state. In this state the F0, F1 and F2 TDA8753A registers are loaded with the values that are in the corresponding line buffers BF0, BF1 and BF2. The first time V50 is issued after power-on, this data is unknown. After a rising UPCL edge has been detected, the address reception state is entered. ADDRESS RECEPTION STATE Bits are counted at each rising UPCL edge. The next 8 bits received on UPDA line are considered as address bits. The address reception is illustrated in Fig.3. Fig.3 Address reception. handbook, halfpage 1 1 110 01 0 incoming stream first data bit of data value for address F2 register last address bit received first bit received (in this example address received is F2 hex) MBE426 |
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