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TSA5521T Folha de dados(PDF) 6 Page - NXP Semiconductors |
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TSA5521T Folha de dados(HTML) 6 Page - NXP Semiconductors |
6 / 24 page 1996 Oct 10 6 Philips Semiconductors Product specification 1.3 GHz universal bus-controlled TV synthesizer TSA5520; TSA5521 PINNING SYMBOL PIN DESCRIPTION RF 1 RF signal input VEE 2 ground VCC1 3 supply voltage (+5 V) VCC2 4 band switch supply voltage (+12 V) BS4 5 PNP band switch buffer output 4 BS3 6 PNP band switch buffer output 3 BS2 7 PNP band switch buffer output 2 BS1 8 PNP band switch buffer output 1 CP 9 charge-pump output Vtune 10 tuning voltage output SW 11 bus format selection input, I2C-bus or 3-wire LOCK 12 lock detector output SCL 13 serial clock input SDA 14 serial data input/output CE 15 chip enable/address selection input XTAL 16 crystal oscillator input Fig.2 Pin configuration. FUNCTIONAL DESCRIPTION The device is controlled via the I2C-bus or the 3-wire bus depending on the voltage applied to the SW input (pin 11). A HIGH level on the SW input enables the 3-wire bus inputs which are Chip Enable (CE), serial data input (SDA) and serial clock input (SCL). A LOW level on the SW input enables the I2C-bus inputs which are CE [Address Selection (AS) input], serial data input/output (SDA) and serial clock input (SCL). The bus format selection is given in Table 2. I2C-bus mode (SW = LOW); see Table 3 Data bytes can be sent to the device after the address transmission (first byte). Four data bytes are required to fully program the device. The bus receiver has an auto-increment facility which permits the programming of the device within one single transmission (address + 4 data bytes). The device can also be partially programmed providing that the first data byte following the address is Divider Byte 1 (DB1) or the Control Byte (CB). The bits in the data bytes are defined in Table 3. The first bit of the first data byte transmitted indicates whether frequency data (first bit = 0) or control and band switch data (first bit = 1) will follow. Until an I2C-bus STOP command is sent by the controller, additional data bytes can be entered without the need to re-address the device. The frequency register is loaded after the 8th clock pulse of the second Divider Byte (DB2), the control register is loaded after the 8th clock pulse of the Control Byte (CB) and the band switch register is loaded after the 8th clock pulse of the Band switch Byte (BB). I2C-bus address selection The module address contains programmable address bits (MA1 and MA0) which offer the possibility of having several synthesizers (up to 3) in one system by applying a specific voltage to the CE input. The relationship between MA1 and MA0 and the input voltage applied to the CE input is given in Table 5. |
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