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CS8420-DSZ Folha de dados(PDF) 3 Page - Cirrus Logic |
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CS8420-DSZ Folha de dados(HTML) 3 Page - Cirrus Logic |
3 / 94 page DS245F4 3 CS8420 10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) ..................................................... 42 10.14 Receiver Channel Status (0Fh) (Read Only) ............................................................................. 43 10.15 Receiver Error (10h) (Read Only) .............................................................................................. 44 10.16 Receiver Error Mask (11h) ......................................................................................................... 45 10.17 Channel Status Data Buffer Control (12h) .................................................................................45 10.18 User Data Buffer Control (13h) .................................................................................................. 46 10.19 Sample Rate Ratio (1Eh) (Read Only) ....................................................................................... 47 10.20 C-Bit or U-Bit Data Buffer (20h - 37h) ........................................................................................ 47 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ............................................................... 47 11. SYSTEM AND APPLICATIONS ISSUES ........................................................................................... 48 11.1 Reset, Power Down and Start-up Options ................................................................................... 48 11.2 Transmitter Startup ...................................................................................................................... 48 11.3 SRC Invalid State ......................................................................................................................... 49 11.4 C/U Buffer Data Corruption .......................................................................................................... 49 11.5 Block-Mode U-Data D-to-E Buffer Transfers ............................................................................... 50 11.6 ID Code and Revision Code ........................................................................................................ 50 11.7 Power Supply, Grounding, and PCB layout ................................................................................. 50 11.8 Synchronization of Multiple CS8420s .......................................................................................... 50 11.9 Extended Range Sample Rate Conversion ................................................................................. 50 12. SOFTWARE MODE - PIN DESCRIPTION ......................................................................................... 51 13. HARDWARE MODES ......................................................................................................................... 55 13.1 Overall Description ....................................................................................................................... 55 13.1.1 Hardware Mode Definitions ................................................................................................. 55 13.1.2 Serial Audio Port Formats ................................................................................................... 55 13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) ............................................ 56 13.2.1 Pin Description - Hardware Mode 1 .................................................................................... 57 13.3 Hardware Mode 2 Description ..................................................................................................... 59 13.3.1 Pin Description - Hardware Mode 2 .................................................................................... 61 13.4 Hardware Mode 3 Description ..................................................................................................... 63 13.4.1 Pin Description - Hardware Mode 3 .................................................................................... 65 13.5 Hardware Mode 4 Description ..................................................................................................... 67 13.5.1 Pin Description - Hardware Mode 4 .................................................................................... 69 13.6 Hardware Mode 5 Description ..................................................................................................... 71 13.6.1 Pin Description - Hardware Mode 5 .................................................................................... 72 13.7 Hardware Mode 6 Description ..................................................................................................... 74 13.7.1 Pin Description - Hardware Mode 6 .................................................................................... 76 14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS ................ 78 14.1 AES3 Transmitter External Components ..................................................................................... 78 14.2 AES3 Receiver External Components .........................................................................................79 14.3 Isolating Transformer Requirements ............................................................................................ 80 15. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT .................................................. 81 15.1 AES3 Channel Status(C) Bit Management .................................................................................. 81 15.1.1 Manually Accessing the E Buffer .........................................................................................82 15.1.2 Reserving the First 5 Bytes in the E Buffer ......................................................................... 83 15.1.3 Serial Copy Management System (SCMS) ......................................................................... 83 15.1.4 Channel Status Data E Buffer Access ................................................................................. 83 15.1.5 One-Byte Mode ................................................................................................................... 84 15.1.6 Two-Byte Mode ................................................................................................................... 84 15.2 AES3 User (U) Bit Management .................................................................................................. 84 15.2.1 Mode 1: Transmit All Zeros ................................................................................................. 84 15.2.2 Mode 2: Block Mode ............................................................................................................ 84 15.2.3 IEC60958 Recommended U Data Format for Consumer Applications ............................... 85 15.2.4 Mode (3): Reserved ............................................................................................................. 85 15.2.5 Mode (4): IEC Consumer B ................................................................................................. 85 |
Nº de peça semelhante - CS8420-DSZ |
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Descrição semelhante - CS8420-DSZ |
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