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SI5367A-B-GQ Folha de dados(PDF) 11 Page - Silicon Laboratories

Nome de Peças SI5367A-B-GQ
Descrição Electrónicos  關P-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
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Fabricante Electrônico  SILABS [Silicon Laboratories]
Página de início  http://www.silabs.com
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Si5367
Preliminary Rev. 0.3
11
71
SDI
I
LVCMOS
Serial Data In.
In SPI microprocessor control mode (CMODE = 1), this
pin functions as the serial data input.
In I2C microprocessor control mode (CMODE = 0), this
pin is ignored.
This pin has a weak pull-down.
77
78
CKOUT3+
CKOUT3–
OMULTI
Clock Output 3.
Differential clock output. Output signal format is selected
by SFOUT3_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
82
83
CKOUT1–
CKOUT1+
OMULTI
Clock Output 1.
Differential clock output. Output signal format is selected
by SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
87
88
CKOUT5–
CKOUT5+
OMULTI
Clock Output 5.
Differential clock output. Output signal format is selected
by SFOUT5_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
90
CMODE
I
3-Level
Control Mode.
Selects I2C or SPI control mode for the device.
0=I2C Control Mode.
1 = SPI Control Mode.
92
93
CKOUT2+
CKOUT2–
OMULTI
Clock Output 2.
Differential clock output. Output signal format is selected
by SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
97
98
CKOUT4–
CKOUT4+
OMULTI
Clock Output 4.
Differential clock output. Output signal format is selected
by SFOUT4_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended
clock outputs.
GND PAD
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electri-
cal impedance to a ground plane.
Table 3. Si5367 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5368 Register Map.


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