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SI8430-A-IS Folha de dados(PDF) 6 Page - Silicon Laboratories |
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SI8430-A-IS Folha de dados(HTML) 6 Page - Silicon Laboratories |
6 / 30 page Si8430/31/35 6 Rev. 0.3 Figure 1. ENABLE Timing Diagram Figure 2. Propagation Delay Timing For All Models Output Rise Time tr CL = 15 pF See Figure 2 —2 — ns Output Fall Time tf CL = 15 pF See Figure 2 —2 — ns Common Mode Transient Immunity CTMI VI =VDD or 0 V 25 30 — kV/µs Enable to Data Valid ten1 See Figure 1 — 5 — ns Enable to Data Tri-State ten2 See Figure 1 — 5 — ns Start-up Time2 tSU —3 — µs Notes: 1. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, load, and ambient temperature. 2. Start-up time is the time period from the application of power to valid data at the output. Table 1. Electrical Characteristics (Continued) (VDD1 = 5 V, VDD2 = 5 V, TA = –40 to 125 ºC) Parameter Symbol Test Condition Min Typ Max Unit ENABLE OUTPUTS ten1 ten2 Typical Input tPLH tPHL Typical Output tr tf 90% 10% 90% 10% 50% 50% |
Nº de peça semelhante - SI8430-A-IS |
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Descrição semelhante - SI8430-A-IS |
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