© 2006 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN5109B Rev. 1.0.0

3 of 14

Pin Configuration

Figure 3. Pin Assignments

Pin Definitions

Pin #

Name

Description

1

BOOT

Bootstrap Supply Input

. Provides voltage supply to the high-side MOSFET driver. Connect

to the bootstrap capacitor (see the Applications section).

2

PWM

PWM Signal Input

. This pin accepts a logic-level PWM signal from the controller.

3

OD

Output Disable

. When LOW, this pin disables FET switching (HDRV and LDRV are held

LOW). (Also referred to as OD#.)

4

VCC

Power Input

. +12V chip bias power. Bypass with a 1

μF ceramic capacitor.

5

LDRV

Low-Side Gate Drive Output

. Connect to the gate of low-side power MOSFET(s).

6

PGND

Power ground

. Connect directly to the source of the low-side MOSFET(s).

7

SW

Switch Node Input

. Connect as shown in Figure 1. SW provides return for the high-side

bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

8

HDRV

High-Side Gate Drive Output

. Connect to the gate of high-side power MOSFET(s).

BOOT

PWM

OD

VCC

FAN

5009

1

2

3

4

8

7

6

5

HDRV

SW

PGND

LDRV