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FM18L08-70-TG Folha de dados(PDF) 4 Page - Ramtron International Corporation |
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FM18L08-70-TG Folha de dados(HTML) 4 Page - Ramtron International Corporation |
4 / 13 page FM18L08 Rev. 3.4 July 2007 4 of 13 must remain high for at least the minimum precharge timing specification. The user dictates the beginning of this operation since a precharge will not begin until /CE rises. However, the device has a maximum /CE low time specification that must be satisfied. FRAM Design Considerations When designing with FRAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide FRAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use FRAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a low transition of /CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM18L08. The reason for /CE to strobe for each address is two- fold: it latches the new address and creates the necessary precharge period while /CE is high. Address 1 Address 2 Data 1 Data 2 Valid Memory Signaling Relationship CE Address Data FRAM signaling Address 2 Data 1 CE Address Data SRAM signaling Invalid Memory Signaling Relationship Address 1 Data 2 Figure 2. Memory Address Relationships |
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