FM25040A datasheet(6/13 Pages) RAMTRON

Nome de Peças	FM25040A

Descrição Electrónicos	4Kb FRAM Serial Memory

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Fabricante Electrônico	RAMTRON [Ramtron International Corporation]

Página de início	http://www.ramtron.com

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6 / 13 page

FM25040A

Rev. 3.0

May 2006

Page 6 of

13

RDSR - Read Status Register

The RDSR command allows the bus master to verify

the contents of the Status Register. Reading Status

provides information about the current state of the

write protection features. Following the RDSR op-

code, the FM25040A will return one byte with the

contents of the Status Register. The Status Register is

described in detail in the Status Register & Write

Protection section.

WRSR – Write Status Register

The WRSR command allows the user to select

certain write protection features by writing a byte to

the Status Register. Prior to issuing a WRSR

command, the /WP pin must be high or inactive. Note

that on the FM25040A, /WP prevents writing to the

Status Register and the memory array. Prior to

sending the WRSR command, the user must send a

WREN command to enable writes. Note that

executing a WRSR command is a write operation and

therefore clears the Write Enable Latch. The bus

timing for RDSR and WRSR are shown below.

Figure 7. RDSR Bus Timing

Figure 8. WRSR Bus Timing

Status Register & Write Protection

The write protection features of the FM25040A are

multi-tiered. First, a WREN op-code must be issued

prior to any write operation. Assuming that writes

are enabled using WREN, writes to memory are

controlled by the /WP pin and the Status Register.

When /WP is low, the entire part is write-protected.

When /WP is high, the memory protection is subject

to the Status register. Writes to the Status Register

are

performed

using the

WREN

and

WRSR

commands and subject to the /WP pin. The Status

Register is organized as follows.

Table 2. Status Register

Bit

7

6

5

4

3

2

1

0

Name

0

BP1

BP0

WEL

0

Bits 0 and 4-7 are fixed at 0 and cannot be modified.

Note that bit 0 (/RDY in EEPROMs) is wired low

since FRAM writes have no delay and the memory is

never busy. All EEPROMs use Ready to indicate

whether a write cycle is complete or not. The BP1 and

BP0 bits control write protection features. They are

nonvolatile (shaded yellow). The WEL flag indicates

the state of the Write Enable Latch. This bit is

internally set by the WREN command and is cleared

by terminating a write cycle (/CS high) or by using

the WRDI command.

BP1 and BP0 are memory block write protection bits.

They specify portions of memory that are write-

protected as shown in the following table.

Table 3. Block Memory Write Protection

BP1

BP0

Protected Address Range

0

None

0

1

180h to 1FFh (upper ¼)

1

0

100h to 1FFH (upper ½)

1

000h to 1FFh (all)

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