Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

CAT24C128WI-GT3 Folha de dados(PDF) 4 Page - Catalyst Semiconductor

Nome de Peças CAT24C128WI-GT3
Descrição Electrónicos  128-Kb I2C CMOS Serial EEPROM
Download  18 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  CATALYST [Catalyst Semiconductor]
Página de início  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT24C128WI-GT3 Folha de dados(HTML) 4 Page - Catalyst Semiconductor

  CAT24C128WI-GT3 Datasheet HTML 1Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 2Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 3Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 4Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 5Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 6Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 7Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 8Page - Catalyst Semiconductor CAT24C128WI-GT3 Datasheet HTML 9Page - Catalyst Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 4 / 18 page
background image
CAT24C128
4
Doc. No. MD-1103, Rev. J
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER-ON RESET (POR)
The CAT24C128 incorporates Power-On Reset
(POR) circuitry which protects the device against
powering up in the wrong state.
The CAT24C128 will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device
address. When not driven, these pins are pulled LOW
internally.
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24C128 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock
and all START and STOP conditions. The CAT24C128
acts as a Slave device. Master and Slave alternate as
either transmitter or receiver. Up to 8 devices may be
connected to the bus as determined by the device ad-
dress inputs A0, A1, and A2.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. The first 4 bits of the Slave
address are set to 1010, for normal Read/Write opera-
tions (Figure 2). The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices and must match the
state of the external address pins. The last bit, R/W,
specifies whether a Read (1) or Write (0) operation is
to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge all address bytes and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowl-
edges the data, the Slave will continue transmitting. The
Master terminates the session by not acknowledging
the last data byte (NoACK) and by issuing a STOP
condition. Bus timing is illustrated in Figure 4.


Nº de peça semelhante - CAT24C128WI-GT3

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
Catalyst Semiconductor
CAT24C128WI-GT3 CATALYST-CAT24C128WI-GT3 Datasheet
520Kb / 17P
   128-Kb I2C CMOS Serial EEPROM
logo
ON Semiconductor
CAT24C128WI-GT3 ONSEMI-CAT24C128WI-GT3 Datasheet
166Kb / 14P
   128 kb I2C CMOS Serial EEPROM
September, 2009 ??Rev. 11
CAT24C128WI-GT3 ONSEMI-CAT24C128WI-GT3 Datasheet
181Kb / 16P
   128 kb I2C CMOS Serial
August, 2013 ??Rev. 15
More results

Descrição semelhante - CAT24C128WI-GT3

Fabricante ElectrônicoNome de PeçasFolha de dadosDescrição Electrónicos
logo
Catalyst Semiconductor
CAT24C128 CATALYST-CAT24C128 Datasheet
520Kb / 17P
   128-Kb I2C CMOS Serial EEPROM
logo
ON Semiconductor
CAT24C128 ONSEMI-CAT24C128 Datasheet
166Kb / 14P
   128 kb I2C CMOS Serial EEPROM
September, 2009 ??Rev. 11
CAV24C128 ONSEMI-CAV24C128_18 Datasheet
269Kb / 16P
   EEPROM Serial 128-Kb I2C
May, 2018 ??Rev. 1
CAT24C128HU4IGT3 ONSEMI-CAT24C128HU4IGT3 Datasheet
181Kb / 16P
   128 kb I2C CMOS Serial
August, 2013 ??Rev. 15
CAT25128 ONSEMI-CAT25128 Datasheet
186Kb / 16P
   128-Kb SPI Serial CMOS EEPROM
February, 2010 ??Rev. 2
CAT25128LI-G ONSEMI-CAT25128LI-G Datasheet
216Kb / 20P
   128-Kb SPI Serial CMOS EEPROM
September, 2012 ??Rev. 7
CAT25128VI-G ONSEMI-CAT25128VI-G Datasheet
216Kb / 20P
   128-Kb SPI Serial CMOS EEPROM
September, 2012 ??Rev. 7
CAT25128 ONSEMI-CAT25128_12 Datasheet
216Kb / 20P
   128-Kb SPI Serial CMOS EEPROM
September, 2012 ??Rev. 7
CAT25128 ONSEMI-CAT25128_14 Datasheet
220Kb / 20P
   128-Kb SPI Serial CMOS EEPROM
February, 2014 ??Rev. 8
CAT24S128 ONSEMI-CAT24S128 Datasheet
96Kb / 12P
   128 Kb I2C CMOS Serial EEPROM with Software Write Protect
September, 2018 ??Rev. 7
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


Folha de dados Download

Go To PDF Page


Ligação URL




Privacy Policy
ALLDATASHEETPT.COM
ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com