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CAT25040YE-GT3 Folha de dados(PDF) 9 Page - Catalyst Semiconductor

Nome de Peças CAT25040YE-GT3
Descrição Electrónicos  1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM
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Fabricante Electrônico  CATALYST [Catalyst Semiconductor]
Página de início  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT25040YE-GT3 Folha de dados(HTML) 9 Page - Catalyst Semiconductor

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CAT25010, CAT25020, CAT25040
© Catalyst Semiconductor, Inc.
9
Doc. No. MD-1006 Rev. T
Characteristics subject to change without notice
READ OPERATIONS
Read from Memory Array
To read from memory, the host sends a READ
instruction followed by a 8-bit address (for the
CAT25040, bit 3 of the read instruction opcode
contains A8 address bit).
After
receiving
the
last
address
bit,
the
CAT25010/20/40 will respond by shifting out data on
the SO pin (as shown in Figure 8). Sequentially stored
data can be read out by simply continuing to run the
clock. The internal address pointer is automatically
incremented to the next higher address as data is
shifted out. After reaching the highest memory
address, the address counter “rolls over” to the lowest
memory address, and the read cycle can be continued
indefinitely. The read operation is terminated by taking
CS
¯¯ high.
Read Status Register
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT25010/20/40 will shift out the
contents of the status register on the SO pin
(Figure 9). The status register may be read at any
time, including during an internal write cycle.
Figure 8. READ Timing
Notes:
Dashed Line = mode (1, 1) - - - - - -
* X = 0 for CAT25010, CAT25020. X = A8 for CAT25040
Figure 9. RDSR Timing
Note:
Dashed Line = mode (1, 1) - - - - - -
01
2
3
4
5
6
7
8
10
911
12
13
14
SCK
SI
DATA OUT
MSB
HIGH IMPEDANCE
OPCODE
SO
7
6
5
4
3
2
1
0
CS
00
0
00
1
0
1
SCK
SI
SO
BYTE ADDRESS
01
23
456
78
9
D7 D6 D5 D4 D3 D2 D1 D0
CS
DATA OUT
MSB
HIGH IMPEDANCE
A0
OPCODE
13
12
14 15
16
17
18 19
20
21 22
00
00
X*
0
1
1
A7


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