SN54HC259, SN74HC259

8BIT ADDRESSABLE LATCHES

SCLS134E − DECEMBER 1982 − REVISED SEPTEMBER 2003

4

POST OFFICE BOX 655303

logic diagram, each internal latch (positive logic)

C

R

TG

C

C

C

C

TG

C

C

D

Q

−0.5 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±20 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±25 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance,

73

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package

67

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package

64

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package

108

°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54HC259

SN74HC259

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

2

5

6

2

5

6

V

VCC = 2 V

1.5

1.5

VIH

High-level input voltage

VCC = 4.5 V

3.15

3.15

V

VIH

High-level input voltage

VCC = 6 V

4.2

4.2

V

VCC = 2 V

0.5

0.5

VIL

Low-level input voltage

VCC = 4.5 V

1.35

1.35

V

VIL

Low-level input voltage

VCC = 6 V

1.8

1.8

V

VI

Input voltage

0

VCC

0

VCC

V

VO

Output voltage

0

VCC

0

VCC

V

VCC = 2 V

1000

1000

∆t/∆v

Input transition rise/fall time

VCC = 4.5 V

500

500

ns

∆t/∆v

Input transition rise/fall time

VCC = 6 V

400

400

ns

TA

Operating free-air temperature

−55

125

−40

85

°C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.