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74VHC112SJ Folha de dados(PDF) 5 Page - Fairchild Semiconductor

Nome de Peças 74VHC112SJ
Descrição Electrónicos  Dual J-K Flip-Flops with Preset and Clear
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Fabricante Electrônico  FAIRCHILD [Fairchild Semiconductor]
Página de início  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74VHC112SJ Folha de dados(HTML) 5 Page - Fairchild Semiconductor

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©1995 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74VHC112 Rev. 1.2
5
AC Electrical Characteristics
Note:
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load. Average operating current can be obtained from the equation:
ICC (opr.) = CPD • VCC • fIN + ICC / 4 (per F/F), and the total CPD when n pcs of the Flip-Flop operate can be calculated
by the following equation: CPD (total) = 30 + 14 • n
AC Operating Requirements
Note:
3. VCC is 3.3 ± 0.3V or 5.0 ± 0.5V.
Symbol
Parameter
VCC (V)
Conditions
TA = 25°C
TA = –40°C
to +85°C
Units
Min.
Typ.
Max.
Min.
Max.
fMAX
Maximum Clock
Frequency
3.3 ± 0.3
CL = 15pF
110
150
100
MHz
CL = 50pF
90
120
80
5.0 ± 0.5
CL = 15pF
150
200
135
MHz
CL = 50pF
120
185
110
tPLH, tPHL
Propagation Delay Time
(CP to Qn or Qn)
3.3 ± 0.3
CL = 15pF
8.5
11.0
1.0
13.4
ns
CL = 50pF
10.0
15.0
1.0
16.5
5.0 ± 0.5
CL = 15pF
5.1
7.3
1.0
8.8
ns
CL = 50pF
6.3
10.5
1.0
12.0
tPLH, tPHL
Propagation Delay Time
(PR or CLR to Qn or Qn)
3.3 ± 0.3
CL = 15pF
6.7
10.2
1.0
11.7
ns
CL = 50pF
9.7
13.5
1.0
15.0
5.0 ± 0.5
CL = 15pF
4.6
6.7
1.0
8.0
ns
CL = 50pF
6.4
9.5
1.0
11.0
CIN
Input Capacitance
VCC = Open
4
10
10
pF
CPD
Power Dissipation
Capacitance
(2)
18
pF
Symbol
Parameter
VCC (V)
(3)
TA = 25°C
TA = –40°C to +85°C
Units
Typ.
Guaranteed Minimum
tW
Minimum Pulse Width
(CP or CLR or PR)
3.3
5.0
5.0
ns
5.0
5.0
5.0
tS
Minimum Setup Time
(Jn or Kn to CPn)
3.3
5.0
5.0
ns
5.0
4.0
4.0
tH
Minimum Hold Time
(Jn or Kn to CPn)
3.3
1.0
1.0
ns
5.0
1.0
1.0
tREC
Minimum Recovery Time
(CLR or PR to CP)
3.3
6.0
6.0
ns
5.0
5.0
5.0


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