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FEATURES

RGY PACKAGE

(TOP VIEW)

1

14

7

8

2

3

4

5

6

13

12

11

10

9

4B

4A

4Y

3B

3A

1B

1Y

2A

2B

2Y

DESCRIPTION/ORDERING INFORMATION

A

B

Y

SN74AUC00

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SCES510A – NOVEMBER 2003 – REVISED MARCH 2005

•

Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

•

Operation

•

Sub-1-V Operable

•

•

Low Power Consumption, 10-

µA Max I

CC

•

±8-mA Output Drive at 1.8 V

•

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

The SN74AUC00 devices perform the Boolean function Y = A

⋅ B or Y = A + B in positive logic.

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

QFN – RGY

Tape and reel

SN74AUC00RGYR

MS00

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(EACH GATE)

INPUTS

OUTPUT

Y

A

B

H

H

L

L

X

H

X

L

H

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2003–2005, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.