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SM34020APCM40 Folha de dados(PDF) 5 Page - Texas Instruments

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Nome de Peças SM34020APCM40
Descrição Electrónicos  GRAPHICS SYSTEM PROCESSOR
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SM34020APCM40 Folha de dados(HTML) 5 Page - Texas Instruments

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SM34020APCM40
GRAPHICS SYSTEM PROCESSOR
SGLS361 − JULY 2006
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME
TYPE†
DESCRIPTION
DRAM and VRAM Control (continued)
WE
O
Write enable. The active low WE drives the WE inputs of DRAMs and VRAMs. WE can also be used as the
active-low write enable to static memories and other devices connected to the SM34020APCM40 local interface.
During a local-memory read cycle, WE remains inactive high while CAS is strobed active low. During a
local-memory write cycle, WE is strobed active low before CAS. During VRAM serial data register transfer cycles,
the state of WE at the falling edge of RAS controls the direction of the transfer.
Host Interface
HA5 − HA31
I
Host address. A host can access a long word by placing the address on these lines. HA5 − HA31 correspond to
LAD5 − LAD31 that output the address to the local memory.
HBS0 − HBS3
I
Host byte selects. HBS0 − HBS3 identify which bytes within the long word are being selected.
HCS
I
Host chip select. A host drives HCS low to latch the current host address present on HA5 − HA31 and the host byte
selects on HBS0 − HBS3. HCS also enables host access cycles to the SM34020APCM40 I/O registers or local
memory. During the low-to-high transition of RESET, the level on HCS determines whether the SM34020APCM40
is halted (HCS is high for host-present mode) or whether it begins executing its reset service routine (HCS is low
for self-bootstrap mode).
HDST
O
Host data-latch strobe. The rising edge of HDST latches data from the SM34020APCM40 local address space to
the external host data latch on host read accesses. HDST can be used in conjunction with HRDY to indicate that
data is valid in the external data latch.
HINT
O
Host Interrupt. HINT allows the SM34020APCM40 to interrupt a host by setting the INTOUT bit in the HSTCTLL
I/O register. HINT can also be used to interrupt the host if a BUSFLT or RETRY occurs due to a host access cycle.
HOE
O
Host data latch output enable. HOE enables data from host data latches to the SM34020APCM40 local address
space on host write cycles. HOE can be used in conjunction with HRDY to indicate data has been written to memory
from the external data latch.
HRDY
O
Host ready. HRDY is normally low and goes high to indicate that the SM34020APCM40 is ready to complete a
host-initiated read or write cycle. If the SM34020APCM40 is ready to accept the access request, HRDY is driven
high and the host can proceed with the access. A host can use HRDY logically combined with HDST and HOE to
determine when the local bus access cycles have completed.
HREAD
I
Host read strobe. HREAD is driven low during a read request from a host processor. This notifies the
SM34020APCM40 that the host is requesting access to the I/O registers or to local memory. HREAD should not
be asserted at the same time that HWRITE is asserted.
HWRITE
I
Host write strobe. HWRITE is driven low to indicate a write request by a host processor. This notifies the
SM34020APCM40 that a write request is pending. The rising edge of HWRITE is used to indicate that the host has
latched data to be written in the external data transceivers. HWRITE should not be asserted at the same time
HREAD is asserted.
System Control
CLKIN
I
Clock input. CLKIN generates LCLK1 and LCLK2, to which all processor functions in the SM34020APCM40 are
synchronous. A separate asynchronous input clock (VCLK) controls the video timing and video registers.
LCLK1, LCLK2
O
Local output clocks. LCLK1 and LCLK2 are 90 degrees out of phase with each other. They provide convenient
synchronous control of external circuitry to the internal timing. All signals output from the SM34020APCM40
(except the CRT timing signals) are synchronous to LCLK1 and LCLK2.
LINT1, LINT2
I
Local interrupt requests. Interrupts from external devices are transmitted to the SM34020APCM40 on LINT1 and
LINT2. Each local interrupt signal activates the request for one of two interrupt request levels. An external device
generates an interrupt request by driving the appropriate interrupt request pin to its active-low state. LINT1, LINT2
should remain low until the SM34020APCM40 recognizes it. LINT1, LINT2 can be applied asynchronously to the
SM34020APCM40 as they are synchronized internally before use.
RESET
I
System reset. During normal operation, RESET is driven low to reset the SM34020APCM40. When RESET is
asserted low, the SM34020APCM40 internal registers are set to an initial known state and all output and
bidirectional pins are driven either to inactive levels or to the high-impedance state. The SM34020APCM40
behavior following reset depends on the level of the HCS input just before the low-to-high transition of RESET. If
HCS is low, the SM34020APCM40 begins executing the instructions pointed to by the reset vector. If HCS is high,
the SM34020APCM40 is halted until a host processor writes a 0 to the HLT bit in the HSTCTLL register.
† I = input, O = output


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