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SM5964AL25 Folha de dados(PDF) 9 Page - SyncMOS Technologies,Inc |
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SM5964AL25 Folha de dados(HTML) 9 Page - SyncMOS Technologies,Inc |
9 / 30 page SyncMOS Technologies International, Inc. SM5964A 8-Bit Micro-controller With 64KB ISP Flash & TWSI & PWM & 1KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. Ver 2.3 SM5964A 10/2006 9 AC Characteristic VCC=3.3V±10%, VSS=0V, tclk min = 1/ fmax(maximum operating frequency) TA=0 to + ℃ 70℃ CL=100pF for Port0, ALE and /PSEN; CL=80pF for all other outputs unless otherwise specified. Symbol FIGURE PARAMETER MIN MAX UNIT External Clock drive into XTAL1 tCLK 4 Xtal1 Period 40(1) - ns tCLKH 4 Xtal1 HIGH time 20 - ns tCLKL 4 Xtal1 LOW time 20 - ns tCLKR 4 XTAL1 rise time - 10 ns tCLKF 4 XTAL1 fall time - 10 ns tCYC 4 Controller cycle time = tCLK / 12 3.33 - ns NOTES : 1. Operating is 25MHz. Symbol FIGURE PARAMETER MIN MAX UNIT Program Memory 1/tCLK 7 System clock frequency 3.0 25 MHz tLHLL 7 ALE pulse width 2tCLK-40 ns tAVLL 7 Address valid to ALE low tCLK-40 ns tLLAX 7 Address hold after ALE low tCLK-30 ns tLLIV 7 ALE LOW to valid instruction in 4tCLK-100 ns tLLPL 7 ALE LOW to /PSEN LOW tCLK-30 ns tPLPH 7 /PSEN pulse width 3tCLK-45 ns tPLIV 7 /PSEN LOW to valid instruction in 3tCLK-105 ns tPXIX 7 Input instruction hold after /PSEN 0 ns tPXIZ 7 Input instruction float after /PSEN tCLK -25 ns tAVIV 7 Address to valid instruction in 5tCLK-105 ns tPLAZ 7 /PSEN low to address float 10 ns Data Memory tAVLL 8,9 Address valid to ALE LOW tCLK-40 ns tLLAX 8,9 Address hold after ALE LOW tCLK-35 ns tRLRH 8 /RD pulse width 6tCLK-100 ns tWLWH 9 /WR pulse width 6tCLK-100 ns tRLDV 8 /RD LOW to valid data in 5tCLK-165 ns tRHDX 8 Data hold after /RD 0 ns tRHDZ 8 Data float after /RD 2tCLK-70 ns tLLDV 8 ALE LOW to valid data in 8tCLK-150 ns tAVDV 8 Address to valid data in 9tCLK-165 ns tLLWL 8,9 ALE LOW to /RD or /WR LOW 3tCLK-50 3tCLK+50 ns tAVWL 8,9 Address valid to /WR or /RD LOW 4tCLK-130 ns tQVWX 9 Data valid to /WR transition tCLK-50 ns tQVWH 9 Data before /WR 7tCLK-150 ns tWHQX 9 Data hold after /WR tCLK-50 ns tRLAZ 8 /RD LOW to address float 0 ns tWHLH 8,9 /RD or /WR HIGH to ALE HIGH tCLK-40 tCLK+40 ns UART tXLXL 10 Serial port clock time 12tCLK ns tQVXH 10 Output data setup to clock rising edge 10tCLK-133 ns tXHQX 10 Output data hold after clock rising edge 2tCLK-117 ns tXHDX 10 Input data hold after clock rising edge 0 ns tXHDV 10 Clock rising edge to input data valid 10tCLK-133 ns |
Nº de peça semelhante - SM5964AL25 |
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Descrição semelhante - SM5964AL25 |
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