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SM8052C40 Folha de dados(PDF) 6 Page - SyncMOS Technologies,Inc

Nome de Peças SM8052C40
Descrição Electrónicos  8 - Bit Micro-controller with 4/8KB ROM embedded
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Fabricante Electrônico  SYNCMOS [SyncMOS Technologies,Inc]
Página de início  http://www.syncmos.com.tw
Logo SYNCMOS - SyncMOS Technologies,Inc

SM8052C40 Folha de dados(HTML) 6 Page - SyncMOS Technologies,Inc

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May 2001
Specifications subject to change without notice,contact your sales representatives for the most recent information.
6/16
Ver 1.1
SM8051/8052 07/2005
SyncMOS Technologies Inc.
SM8051/8052
Watch Dog Timer Registers - WDT Control Register (WDTC, $9F)
WDTE : Watch Dog Timer enable bit
CLEAR : Watch Dog Timer reset bit
PS2 ~ PS0 : clock source divider bit
PS [2:0]
Divider (OSC in)
Time Period (ms) @40MHZ
000
8
13.1
001
16
26.21
010
32
52.42
011
64
104.8
100
128
209.71
101
256
419.43
110
512
838.86
111
1024
1677.72
Watch Dog Timer Register - System Control Register (SCONF, $BF)
The bit 7(WDR) of SCONF is Watch Dog Timer Reset bit. It will be set to 1 when reset signal generated
by WDT overflow. User should check WDR bit whenever un-predicted reset happened.
Reduce EMI Function
The SM8051/8052 allows user to reduce the EMI emission by setting 1 to the bit 0 (ALEI) of SCONF register. This
function will inhibit the clock signal in Fosc/6Hz output to the ALE pin. This function is available when there is
no external program memory or no external data RAM in the system.
WDTE
Unused
CLEAR
Unused
Unused
PS2
PS1
PS0
0
*
0
*
*
0
0
0
WDR
Unused
Unused
Unused
Unused
Unused
Unused
ALEI
0
*
*
*
*
*
*
0
Reset
value
MSB
LSB
Reset
value
MSB
LSB
WDR : Watch Dog Timer Reset. When system reset by Watch Dog Timer overflow, WDR will be set to 1
ALEI : ALE output inhibit bit, to reduce EMI


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