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74AUP1T97GF Folha de dados(PDF) 9 Page - NXP Semiconductors |
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74AUP1T97GF Folha de dados(HTML) 9 Page - NXP Semiconductors |
9 / 17 page 74AUP1T97_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 25 October 2007 9 of 17 NXP Semiconductors 74AUP1T97 Low-power configurable gate with voltage-level translator [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(C L × VCC 2 × f o) = sum of the outputs. VCC = 3.0 V to 3.6 V; VI = 2.3 V to 2.7 V tpd propagation delay A, B, C to Y; see Figure 12 [2] CL = 5 pF 1.7 2.8 4.2 0.5 5.3 5.9 ns CL = 10 pF 2.1 3.4 5.0 1.0 6.1 6.8 ns CL = 15 pF 2.4 3.8 5.6 1.0 6.8 7.5 ns CL = 30 pF 3.2 5.0 7.1 1.5 8.5 9.4 ns VCC = 3.0 V to 3.6 V; VI = 3.0 V to 3.6 V tpd propagation delay A, B, C to Y; see Figure 12 [2] CL = 5 pF 1.4 2.7 4.2 0.5 4.7 5.2 ns CL = 10 pF 1.8 3.3 5.0 1.0 5.7 6.3 ns CL = 15 pF 2.1 3.8 5.6 1.0 6.2 6.9 ns CL = 30 pF 2.9 4.9 7.1 1.5 7.8 8.6 ns Tamb = 25 °C CPD power dissipation capacitance fi = 1 MHz; VI = GND to VCC [3] VCC = 2.3 V to 2.7 V - 3.6 - - - - pF VCC = 3.0 V to 3.6 V - 4.3 - - - - pF Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13. Symbol Parameter Conditions 25 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) |
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