www.ti.com

PIN CONFIGURATION

SCLK

SDI

LDAC

AGND

AV

DD

V

-S

REFL

(ThermalPad)

PDN

RST

USB/BTC

GAIN

RSTSEL

NC

1

2

3

4

5

6

18

17

16

15

14

13

DAC8881

DAC8881

SBAS422A – JULY 2007 – REVISED SEPTEMBER 2007

RGE PACKAGE(1)

QFN-24

(TOP VIEW)

(1)

The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left

floating. Keep the thermal pad separate from the digital ground, if possible.

TERMINAL FUNCTIONS

TERMINAL

NO.

NAME

I/O

DESCRIPTION

1

SCLK

I

SPI bus serial clock input

2

SDI

I

SPI bus serial data input

Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input

3

LDAC

I

register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the

DAC latch is updated.

4

AGND

I

Analog ground

5

I

Analog power supply

6

I

Reference low input sense

7

I

Reference high input sense

8

O

Output of output buffer

9

I

Feedback resistor connected to the inverting input of the output buffer.

10

I

Reference low input force

11

I

Reference high input force

12

NC

—

Do not connect.

13

NC

—

Do not connect.

14

RSTSEL

I

= 8000h. If RSTSEL = DGND, then register data = 0000h.

15

GAIN

I

16

USB/BTC

I

complement format when the pin is connected to DGND.

17

RST

I

Reset input (active low). Logic low on this pin causes the device to perform a reset.

18

PDN

I

pin connects to AGND through 10k

Ω resistor.

SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is

19

CS

I

high, SDO is in high-impedance status.

20

SDOSEL

I

from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register

are shifted out from the SDO pin; this is Daisy-Chain mode for daisy chaining communication.

21

I

22

DGND

I

Digital ground

23

SDO

O

SPI bus serial data output. Refer to the Timing Diagrams for further detail.

24

I

Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.

Copyright © 2007, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): DAC8881