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TC59LM818DMB-33 Folha de dados(PDF) 11 Page - Toshiba Semiconductor

Nome de Peças TC59LM818DMB-33
Descrição Electrónicos  MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2
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Fabricante Electrônico  TOSHIBA [Toshiba Semiconductor]
Página de início  http://www.semicon.toshiba.co.jp/eng
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TC59LM818DMB-33 Folha de dados(HTML) 11 Page - Toshiba Semiconductor

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TC59LM818DMB-33,-40
2005-10-19
11/57
Rev 1.4
POWER UP SEQUENCE
(1)
As for PD , being maintained by the low state (
≤ 0.2 V) is desirable before a power-supply injection.
(2)
Apply VDD before or at the same time as VDDQ.
(3)
Apply VDDQ before or at the same time as VREF.
(4)
Start clock (CLK, CLK ) and maintain stable condition for 200
µs (min).
(5)
After stable power and clock, apply DESL and take PD =H.
(6)
Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1)
(7)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8)
Issue two or more Auto-Refresh commands (Note: 1).
(9)
Ready for normal operation after 200 clocks from Extended Mode Register programming.
NOTES:
(1)
Sequence 6, 7 and 8 can be issued in random order.
(2)
L
= Logic Low, H = Logic High
(3)
DQ output is Hi-Z state during power upsequence.
Address
VDD
VDDQ
VREF
DS
QS
(Free Running mode)
2.5V(TYP)
1.5V or 1.8V(TYP)
1/2 VDDQ (TYP)
op-code
EMRS
op-code
MRS
QS
(Uni-QS mode)
EMRS
MRS
Auto Refresh cycle
Normal Operation
Low
DQ
(Input)
Command
CLK
CLK
PD
200us(min)
tPDEX
lPDA
lRSC
lRSC
lREFC
lREFC
lLOCK = 200clock cycle(min)
RDA MRS DESL
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
DESL


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