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TC59LM818DMG-40 Folha de dados(PDF) 1 Page - Toshiba Semiconductor

Nome de Peças TC59LM818DMG-40
Descrição Electrónicos  MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2
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Fabricante Electrônico  TOSHIBA [Toshiba Semiconductor]
Página de início  http://www.semicon.toshiba.co.jp/eng
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TC59LM818DMG-40 Folha de dados(HTML) 1 Page - Toshiba Semiconductor

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TC59LM818DMG-33,-40
2005-10-19
1/57
Rev 1.4
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
288Mbits Network FCRAM2
− 4,194,304-WORDS × 4 BANKS × 18-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMG is Network
FCRAMTM containing 301,989,888 memory cells. TC59LM818DMG is organized as 4,194,304-words
× 4 banks × 18
bits. TC59LM818DMG feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM818DMG can operate fast core cycle compared with regular DDR SDRAM.
TC59LM818DMG is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
TC59LM818DMG
PARAMETER
-33
-40
CL
= 4
4.5 ns
5.0 ns
CL
= 5
3.75 ns
4.5 ns
tCK
Clock Cycle Time (min)
CL
= 6
3.33 ns
4.0 ns
tRC
Random Read/Write Cycle Time (min)
22.5 ns
25 ns
tRAC Random Access Time (max)
22.5 ns
25 ns
IDD1S Operating Current (single bank) (max)
235 mA
210 mA
lDD2P Power Down Current (max)
65 mA
60 mA
lDD6
Self-Refresh Current (max)
15 mA
15 mA
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs
CS
, FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.33 ns minimum
Clock: 300 MHz maximum
Data:
600 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Selectable Data Strobe
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS
Latency
= 4, 5, 6
Burst Length
= 2, 4
• Organization: 4,194,304 words × 4 banks × 18 bits
• Power Supply Voltage VDD:
2.5 V
± 0.125V
VDDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL
• Package:
60Ball BGA, 1mm
× 1mm Ball pitch (P-BGA60-0917-1.00AZ)
• Lead-Free
Notice: FCRAM is trademark of Fujitsu limited, Japan.
Lead-Free


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