TD7623AFN

2001-03-01 8/19

Figure 3. 3-wire bus data format

l 27-bit DATA TRANSMISSION

During a high level of the enable signal, the data is clocked into the register on the falling edge of the

clock.

The clock number during a high level of the enable signal must be set to 27-bit or more of clock and data

transmission.

The data are latched at the 27th falling edge of the clock signal, validating the previous 27-bit data.

The 4-bit bandswitch data are latched at the 5th bit rising edge of the clock signal, and the data is

updated.

The programmable counter data are latched at the 20th bit rising edge of the clock signal, and the data

is updated.

The control data are latched at the 27th bit falling edge of the clock signal, and the data is updated.

Details of the data timing, see the data timing chart. (Figure 1)