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TLP114A Folha de dados(PDF) 4 Page - Toshiba Semiconductor |
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TLP114A Folha de dados(HTML) 4 Page - Toshiba Semiconductor |
4 / 7 page TLP114A 2007-10-01 4 (Note 5) Device considered a two −terminal device: Pins 1 and 3 shorted together, and pins 4, 5 and 6 shorted together. (Note 6) Maximum electrostatic discharge voltage for any pins: 100V(C=200pF, R=0) Test Circuit 1: Switching Time Test Circuit Test Circuit =2: Common Mode Transient Immunity Test Circuit s) ( r t 320(V) L CM , s) ( r t 320(V) H CM μ = μ = VO IF 5V 1.5V 0 VOL tpLH tpHL 1.5V PW = 100μs DUTY RATIO = 1/10 IF MONITOR PULSE INPUT OUTPUT MONITOR VO VCC = 5V 1 3 4 5 6 RL IF VO VCM 400V 0V 90% 5V 2V 0.8V VOL tr tf 10% VO (IF = 16mA) (IF = 0mA) IF PULSE GEN ZO = 50Ω VCM OUTPUT MONITOR VO VCC = 5V 1 3 4 5 6 RL |
Nº de peça semelhante - TLP114A_07 |
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Descrição semelhante - TLP114A_07 |
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