74AC11162

SYNCHRONOUS 4-BIT DECADE COUNTER

SCAS381 – D3199, AUGUST 1988 – REVISED APRIL 1993

POST OFFICE BOX 655303

3

logic diagram (positive logic)

LOAD

1

10

RCO

M1

G2

1,2T/1C3

G4

3D

4R

M1

G2

1,2T/1C3

G4

3D

4R

M1

G2

1,2T/1C3

G4

3D

4R

M1

G2

1,2T/1C3

G4

3D

4R

2

QA

3

QB

8

QC

9

QD

CLR

20

CLK

19

ENP

12

ENT

11

A

18

B

17

C

14

D

13

LD †

CK †

CK

R

LD

† For the sake of simplicity, the routing of the complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals

are shown on the logic diagram of the D/T flip-flops.