Os motores de busca de Datasheet de Componentes eletrônicos |
|
AD5626BRMZ-REEL7 Folha de dados(PDF) 6 Page - Analog Devices |
|
AD5626BRMZ-REEL7 Folha de dados(HTML) 6 Page - Analog Devices |
6 / 20 page AD5626 Rev. 0 | Page 6 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD 1 CS 2 SCLK 3 SDIN 4 VOUT 8 GND 7 CLR 6 LDAC 5 AD5626 TOP VIEW (Not to Scale) VDD 1 SCLK 3 SDIN 4 VOUT 8 GND 7 AD5626 TOP VIEW (Not to Scale) CS 2 CLR 6 LDAC 5 Figure 3. 8-Lead MSOP Pin Configuration Figure 4. 8-Lead LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 VDD Positive Supply. Nominal value 5 V ± 5%. 2 CS Chip Select. Active low input. 3 SCLK Clock Input. Clock input for the internal serial input shift register. 4 SDIN Serial Data Input. Data on this pin is clocked into the internal serial register on positive clock edges of the SCLK pin. The most significant bit (MSB) is loaded first. 5 LDAC Serial Register Data Write to DAC Register. Active low input that writes the serial register data into the DAC register. Asynchronous input. 6 CLR Clear DAC Register. Active low digital input that clears the DAC register to zero, setting the DAC to minimum scale. Asynchronous input. 7 GND Ground. Analog ground for the DAC. This also serves as the digital logic ground reference voltage. 8 VOUT Voltage Output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and power supply variations. Table 5. Control Logic Truth Table1 CS2, 3 CLK2 CLR LD4 Serial Shift Register Function DAC Register Function H X H H No effect Latched L L H H No effect Latched L H H H No effect Latched L ↑+ H H Shift-register-data advanced one bit Latched ↑+ L H H Shift-register-data advanced one bit Latched H X H ↓– No effect Updated with current shift register contents H X H L No effect Transparent H X L X No effect Loaded with all zeros H X ↑+ H No effect Latched all zeros 1 ↑+ indicates a positive logic transition; ↓– indicates a negative logic transition; X = don’t care. 2 CS and CLK are interchangeable. 3 Returning CS high avoids an additional false clock of serial data input. 4 Do not clock in serial data while LD is low. |
Nº de peça semelhante - AD5626BRMZ-REEL7 |
|
Descrição semelhante - AD5626BRMZ-REEL7 |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |