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AD708 Folha de dados(PDF) 11 Page - Analog Devices |
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AD708 Folha de dados(HTML) 11 Page - Analog Devices |
11 / 16 page AD708 Rev. C | Page 11 of 16 OPERATION WITH A GAIN OF −100 To show the outstanding dc precision of the AD708 in a real application, Table 3 shows an error budget calculation for a gain of −100. This configuration is shown in Figure 28. Table 3. Error Sources Maximum Error Contribution AV = 100 (S Grade) (Full Scale: VOUT = 10 V, VIN = 100 mV) VOS 30 μV/100 mV = 300 ppm IOS (100 kΩ)(1 nA)/10 V = 10 ppm Gain (2 kΩ Load) 10 V/(5 × 106)/100 mV = 20 ppm Noise 0.35 mV/100 mV = 4 ppm VOS Drift (0.3 mV/°C)/100 mV = 3 ppm/°C Total Unadjusted Error @ 25°C = 334 ppm > 11 bits −55°C to +125°C = 634 ppm > 10 bits With Offset Calibrated Out @ 25°C = 34 ppm > 14 bits −55°C to +125°C = 334 ppm > 11 bits 1/2 AD708 VOUT VIN + – 100kΩ 1kΩ 1kΩ 2 3 7 4 6 0.1µF 0.1µF +VS –VS Figure 28. Gain of −100 Configuration This error budget assumes no error in the resistor ratio and no error from power supply variation (the 120 dB minimum PSRR of the AD708S makes this a good assumption). The external resistors can cause gain error from mismatch and drift over temperature. HIGH PRECISION PROGRAMMABLE GAIN AMPLIFIER The three op amp programmable gain amplifier shown in Figure 29 takes advantage of the outstanding matching characteristics of the AD708 to achieve high dc precision. S1 S2 A0 A1 S3 S4 S8 S7 +VS –VS S6 S5 AD7502 OUT 1–4 OUT 5–8 1/2 AD708 VINA 1/2 AD708 VINB 10kΩ 100Ω 10kΩ 10kΩ 1kΩ 10kΩ 10kΩ 10kΩ 10kΩ AD707 10kΩ 10kΩ 9.9kΩ RA 9.9kΩ RB Figure 29. Precision PGA The gains of the circuit are controlled by the select lines, A0 and A1, of the AD7502 multiplexer, and are 1, 10, 100, and 1000 in this design. The input stage attains very high dc precision due to the 30 μV maximum offset voltage match of the AD708S and the 1 nA maximum input bias current match. The accuracy is main- tained over temperature because of the ultralow drift performance of the AD708. To achieve 0.1% gain accuracy, along with high common-mode rejection, the circuit should be trimmed. To maximize common-mode rejection 1. Set the select lines for gain = 1 and ground VINB. 2. Apply a precision dc voltage to VINA and trim RA until VO = −VINA to the required precision. 3. Connect VINB to VINA and apply an input voltage equal to the full-scale common mode expected. 4. Trim RB until V B O = 0 V. To minimize gain errors 1. Select gain = 10 with the control lines and apply a differential input voltage. 2. Adjust the 100 Ω potentiometer to VO = 10 VIN (adjust VIN magnitude as necessary). 3. Repeat Step 1 and Step 2 for gain = 100 and gain = 1000, adjusting the 1 kΩ and 10 kΩ potentiometers, respectively. The design shown in Figure 29 should allow for 0.1% gain accuracy and 0.1 μV/V common-mode rejection when ±1% resistors and ±5% potentiometers are used. |
Nº de peça semelhante - AD708 |
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Descrição semelhante - AD708 |
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