INPUT INTERFACE

To drive the external power device three different

possibilities are allowed:

The Logic Level Mode, either direct or inverted,

and the Pulse Transformer Mode

Using the Logic Level Mode (direct) an high level

(referred to COM), at the INPUT pin will start the

Turn on Procedure (i.e. firing an N channel exter-

nal device). A low level (referred to COM) will in-

stead close the OUT2 pin to VSS.

The functioning is reversed in the inverted mode.

To select the direct mode the SELECT pin must

be connected via a capacitor to COM. The in-

verted mode is chosen by connecting the SE-

LECT pin to COM.

(200ns typ.) are filtered out.

In the Pulse Transformer Mode the SELECT pin

will be the reference pin for the signal applied to

the INPUTpin. The positive pulse will start the

TURN ON PROCEDURE, while the negative

TURN-ON PROCEDURE

The firing of the external power device is per-

formed in three steps in order to avoid the most

common problems that can arise.

In each of these steps there are a number of pa-

rameters that can be easily externally presetted to

the requested values.

First Step

In order to avoid cross-conduction between the

external power device in half bridge arrangement

the driver output is activated after an externally

network has to be connected between the DE-

To minimize this interval only a resistor has to be

iting thus the duration to the internal propagation

delay ton.

Second step

To protect the driven device from latch-up at turn-

externally programmable time interval

an appropriate voltage drop has to be imposed,

by mean of a resistive voltage divider, at the

CLAMP_PROG pin according to the following for-

mula:

100nF

LOGIC

OUT2

OUT1

D94IN116B

MON DELAY

CLAMP_PROG

COM

DFW

LOAD

1.2

Ω

5.6

Ω

ON_SENSE

INPUT

12K

Ω

2.2K

Ω

100nF

(*)

1nF

47K

Ω

ON_LEV_PROG

DELAY

100pF

4.7K

Ω

12K

Ω

12K

Ω

100nF

(*)

POSITIVE

SUPPLY

100

µF-35V

100

µF-10V

NEGATIVE

SUPPLY

100nF

SELECT

NOTES:

(*) The capacitor is required if the pin is left floating.

Figure 4. Gate driving waveforms test circuit.

L6353

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