6

FN6072.7

August 29, 2007

will keep the output MOS transistor in the saturation region.

Expected current settings and 7-Bit accuracy occurs when the

output MOS transistor is operating in the saturation region.

Figure 5 shows the internal connection for the output MOS

source of the output transistor. This voltage is equal to

(Equation 2) should be determined (setting equal to 128) so the

Power Supply Sequence

The recommendation for power supply sequence would be

programming has occurred, and then power-down the

control power supplies (CTL, CE).

Verifying the Programmed Value

The following sequence can be used to verify the

supply. To verify the programmed value, follow the steps

below. The ISL45042 will read memory contents and be set

to that value when the CE pin is grounded.

1. Power-up the ISL45042.

3. Change counter value with CTL pin to desired value.

4. CTL = more than 4.9V and 200ms. Counter value

programmed.

5. Change the counter value with CTL pin to a different

value.

6. CE pin = Ground.

7. Check that the output value is the one programmed in

Step 4.

Generating VDD and CE supply from a Larger

Voltage Source

Figure 6). The impedance of this resistor is 400k

Ω to 500kΩ.

If your design is using a resistor divider network to generate

programming) from a larger voltage source, the 400k

Ω

(worst case) resistor needs to be taken into account as a

parallel resistance when the CE pin is connected to this

source. Another design concern is to be able to provide

enough supply current during programming. The ISL45042

draws about 2mA during this process. Recommended

resistor values are shown in Figure 6. This design will result

in an additional 0.83mA quiescent current flowing through

TABLE 1. CALCULATED VCOM OUTPUT VOLTAGES

SETTING VALUE

VOUT

1

5.468

10

5.313

20

5.141

30

4.969

40

4.797

50

4.625

60

4.453

70

4.281

80

4.109

90

3.936

100

3.764

110

3.592

128

3.282

FIGURE 5. OUTPUT CONNECTION CIRCUIT EXAMPLE

RSET

VOUT PIN

R1

R2

AVDD

VSAT

0.5V

ISET PIN

SETTING

128

---------------------------- x

AV

DD

20

------------------

FIGURE 6. APPLICATION GENERATING VDD AND VCE

VOLTAGES

CE LOGIC

2k

Ω

4k

Ω

ISL45042

CE

VCE

ISL45042