Digital Levels and DC Specifications: ADC0808CJ 4.5V

≤V

ADC0808CCJ, ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75

≤V

otherwise noted

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DATA OUTPUTS AND EOC (INTERRUPT)

V

OUT(1)

Logical “1” Output Voltage

I

V

V

V

OUT(0)

Logical “0” Output Voltage

I

0.45

V

V

OUT(0)

Logical “0” Output Voltage EOC

I

0.45

V

I

OUT

TRI-STATE Output Current

V

3

µA

V

µA

Electrical Characteristics

Timing Specifications V

Symbol

Parameter

Conditions

MIn

Typ

Max

Units

t

WS

Minimum Start Pulse Width

(

Figure 5)

100

200

ns

t

WALE

Minimum ALE Pulse Width

(

Figure 5)

100

200

ns

t

s

Minimum Address Set-Up Time

(

Figure 5)25

50

ns

t

H

Minimum Address Hold Time

(

Figure 5)25

50

ns

t

D

Analog MUX Delay Time

R

1

2.5

µS

From ALE

t

OE Control to Q Logic State

C

125

250

ns

t

OE Control to Hi-Z

C

125

250

ns

t

c

Conversion Time

f

90

100

116

µS

f

c

Clock Frequency

10

640

1280

kHz

t

EOC

EOC Delay Time

(

Figure 5)

0

8+2 µS

Clock

Periods

C

IN

Input Capacitance

At Control Inputs

10

15

pF

C

OUT

TRI-STATE Output

At TRI-STATE Outputs

10

15

pF

Capacitance

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating

the device beyond its specified operating conditions.

Note 2: All voltages are measured with respect to GND, unless othewise specified.

Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater

over temperature variations, initial tolerance and loading.

Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See

Figure 2. None of these A/Ds requires a zero or full-scale adjust. How-

ever, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages

can be adjusted to achieve this. See

Figure 13.

Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has little

temperature dependence (

Figure *NO TGT: fig NS0592*). See paragraph 4.0.

Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.

Note 8: Human body model, 100 pF discharged through a 1.5 k

Ω resistor.

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