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M27W064-100N1T Folha de dados(PDF) 7 Page - STMicroelectronics

Nome de Peças M27W064-100N1T
Descrição Electrónicos  64 Mbit 4Mb x16 3V Supply FlexibleROM??Memory
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
Página de início  http://www.st.com
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M27W064
BUS OPERATIONS
There are six standard bus operations that control
the device. These are Bus Read, Bus Write, Out-
put Disable, Standby, Automatic Standby and
Electronic Signature. See Tables 2, Bus Opera-
tions, for a summary. Typically glitches of less
than 5ns on Chip Enable or Write Enable are ig-
nored by the memory and do not affect bus opera-
tions.
Bus Read. Bus Read operations read from the
memory cells, or specific registers in the Com-
mand Interface. A valid Bus Read operation in-
volves setting the desired address on the Address
Inputs and applying a Low signal, VIL, to Chip En-
able and Output Enable. The Data Inputs/Outputs
will output the value, see Figure 10, Read AC
Waveforms, and Table 11, Read AC Characteris-
tics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. Bus Write is enabled only
when VPP is set to VHH. A valid Bus Write opera-
tion begins by setting the desired address on the
Address Inputs. The Address Inputs are latched by
the Command Interface on the falling edge of Chip
Enable. The Data Inputs/Outputs are latched by
the Command Interface on the rising edge of Chip
Enable. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure
11, Write AC Waveforms, and Table 12, Write AC
Characteristics, for details of the timing require-
ments.
Output Disable. The Data Inputs/Outputs are in
the high impedance state when Output Enable is
High, VIH.
Standby. When Chip Enable is High, VIH, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the
Standby Supply Current, ICC2, Chip Enable should
be held within VCC ± 0.2V. For the Standby current
level see Table 10, DC Characteristics.
During program operation the memory will contin-
ue to use the Program Supply Current, ICC3, for
Program operation until the operation completes.
Automatic Standby. If CMOS levels (VCC ± 0.2V)
are used to drive the bus and the bus is inactive for
150ns or more the memory enters Automatic
Standby where the internal Supply Current is re-
duced to the Standby Supply Current, ICC2. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Electronic Signature. The
memory
has
two
codes, the manufacturer code and the device
code, that can be read to identify the memory.
These codes can be read by applying the signals
listed in Tables 2, Bus Operations, once the Auto
Select Command is executed. To exit Electronic
Signature mode, the Read/Reset command must
be issued.
Table 2. Bus Operations
Note: 1. X = VIL or VIH.
2. XX = VIL, VIH or VHH
3. When reading Status Register during Program algorithm execution VPP must be kept at VHH.
Operation
E
G
VPP
Address Inputs
A0-A21
Data Inputs/Outputs
DQ15-DQ0
Bus Read
VIL
VIL
XX(3)
Cell Address
Data Output
Bus Write
VIL
VIH
VHH
Command Address
Data Input
Output Disable
X
VIH
X
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
Code
VIL
VIL
VHH
A0 = VIL, A1 = VIL,
Others VIL or VIH
0020h
Read Device Code
VIL
VIL
VHH
A0 = VIH, A1 = VIL,
Others VIL or VIH
888Ah


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