Data Sheet #: TM084
Page 7 of 44
Rev: P02
Date: 12/5/06
© Copyright 200
6 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC4130
Synchronous Clock for SETS
Data Sheet
Register Map
Table 4: Register Map
Addr
Reg Name
Bits
Type
Description
0x00
Chip_ID
15-0
R
Chip ID, 0x4130
0x02
Chip_Rev
7-0
R
Chip revision number 0x01
0x03
Chip_Sub_Rev
7-0
R
Chip sub-revision 0x01
0x04
T0_T4_MS_Sts
1-0
R
Indicates master/slave state
0x05
T0_Slave_Phase_Adj
11-0
R/W
Adjust T0 slave phase from 0 ~ 409.5 nS in 0.1 nS steps
0x07
T4_Slave_Phase_Adj
11-0
R/W
Adjust T4 slave phase from 0 ~ 409.5 nS in 0.1 nS steps
0x09
Fill_Rate
3-0
R/W
Leaky bucket fill rate, 1 ~ 16 mS
0x0a
Leak_Rate
3-0
R/W
Leaky bucket leak rate, 1/nth of fill rate, n = 1 ~ 16
0x0b
Bucket_Size
5-0
R/W
Leaky bucket size, 0 ~ 63
0x0c
Assert_Threshold
5-0
R/W
Leaky bucket alarm assert threshold, 0 ~ 63
0x0d
De_Assert_Threshold
5-0
R/W
Leaky bucket alarm de-assert threshold, 0 ~ 63
0x0e
Freerun_Cal
10-0
R/W
Freerun calibration of the TCXO, - 102.4 ~ + 102.3 ppm
0x10
Disqualification_Range
9-0
R/W
Reference disqualification range, 0 ~ 102.3 ppm
0x12
Qualification_Range
9-0
R/W
Reference qualification range, 0 ~ 102.3 ppm
0x14
Qualification_Timer
5-0
R/W
Reference qualification timer, 0 ~ 63 S
0x15
Ref_Selector
3-0
R/W
Determines which reference data is shown in register 0x16
0x16
Ref_Frq_Offset
14-0
R
Reference frequency and frequency offset are shown in bits 14-12
and 11-0
0x18
Refs_Activity
13-0
R
Reference and cross reference activity
0x1a
Refs_Qual
11-0
R
Reference 1 ~ 12 qualification
0x1c
T0_Control_Mode
5-0
R/W
OOP -Follow/Don’t Follow, Manual/Auto, Revertive, HO_Usage,
PhaseAlignMode
0x1d
T0_Bandwidth
4-0
R/W
Bandwidth selection
0x1e
T0_Auto_Active_Ref
3-0
R
Indicates automatically selected reference
0x1f
T0_Manual_Active_Ref
3-0
R/W
Selects the active reference in manual mode
0x20
Reserved
31-0
R
Reserved
0x24
T0_Long_Term_Accu_History
31-0
R
Long term Accumulated History for T0 relative to the TCXO
0x28
T0_Short_Term_Accu_History
31-0
R
Short term Accumulated History for T0 relative to the TCXO
0x2c
T0_User_Accu_History
31-0
R/W
User Holdover data for T0 relative to the TCXO
0x30
T0_HO_BW_Ramp
7-0
R/W
Bits7-4, Long term history accumuation bandwidth: 9.7, 4.9, 2.4, 1.2,
0.61, 0.03 mHz
Bits3-2, Short term history accumulation bandwidth: 2.5, 1.24, 0.62,
0.31 mHz
Bit21:0, Ramp control: none, 1, 1.5, 2 ppm/S
0x31
T0_Priority_Table
47-0
R/W
REF1-12 selection priority for automatic mode, 4 bits/reference
0x37
T0_PLL_Status
7-0
R
LTH Avail, LTH Complete, OOP, LOL, LOS, Sync
0x38
T0_Accu_Flush
0-0
W
0: Flush current history, 1: Flush all histories
0x39
T4_Control_Mode
5-0
R/W
OOP -Follow/Don’t Follow, Manual/Auto, Revertive, HO_Usage,
PhaseAlignMode
0x3a
T4_Bandwidth
4-0
R/W
Bandwidth selection
0x3b
T4_Auto_Active_Ref
3-0
R
Indicates automatically selected reference
0x3c
T4_Manual_Active_Ref
3-0
R/W
Selects the active reference in manual mode
0x3d
Reserved
31-0
R
Reserved
0x41
T4_Long_Term_Accu_History
31-0
R
Long term Accumulated History for T4 relative to the TCXO