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STC4130-I Folha de dados(PDF) 9 Page - List of Unclassifed Manufacturers

Nome de Peças STC4130-I
Descrição Electrónicos  Synchronous Clock for SETS
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Data Sheet #: TM084
Page 9 of 44
Rev: P02
Date: 12/5/06
© Copyright 200
6 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC4130
Synchronous Clock for SETS
Data Sheet
General Description
The STC4130 is an integrated single chip solution for
the synchronous clock in SDH and SONET network
elements. It’s highly integrated design implements all
of the necessary reference selection, monitoring, dig-
ital filtering, synthesis, and control functions. An
external OCXO or TCXO at either 10 or 20 MHz com-
pletes a system level solution (see Functional Block
Diagram, Figure 1).
The STC4130 includes two independent DPLLs
(Digital Phase-Locked Loop) implementing the timing
functions of T0 and T4. Each may select one of 12
reference inputs as its active reference. T0 provides
7 of the chip’s 8 clock outputs while T4 provides one
clock output. Both T0 and T4 provide a cross refer-
ence output for master/slave applications.
Reference frequencies are autodected and may each
be 8KHz, 64KHz, 1.544MHz, 2.048MHz, 19.44MHz,
38.88MHz, or 77.76MHz. Each reference input is
continuously monitored for activity and frequency
offset. Activity monitoring is implemented with a leaky
bucket accumulator with programmable fill and leak
rates. Frequency offset is determined relative to the
digitally
calibrated
external
OCXO/TCXO.
A
reference is designated as “qualified” if it is active
and its frequency is within the programmed
frequency offset range for a pre-programmed time.
Active references may be selected manually or
automatically, individually selectable for T0 and T4.
In manual mode, the active reference is selected
under application control,
independant of it’s
qualification status.
In automatic mode, the active reference is selected
according to revertivity status, and each reference’s
priority and qualification. Reference priorities are
individually programmable. T0 and T4 each have
their own priority tables. While a current active
reference is qualified, revertivity determines whether
a higher priority qualified reference
should be
selected as the new active reference. If revertivity is
enabled, the highest priority qualified reference will
always be selected as the active reference. If
revertivity is not enabled, a new or returning qualified
reference of higher priority will not be selected until
the current active reference is disqualified.
The two independent clock generators, T0 and T4,
each include a DPLL, which may operate in the
Freerun, Synchronized, and Holdover modes. Both
clock generators support master/slave operation for
redundant applications. T0 generates Connor-
Winfield’s proprietary SyncLinkTM Cross-couple
data link, which provides master/slave phase
information and state data to ensure seamless side
switches. T4 provides an 8KHz cross-couple signal.
The slave output clock phase is user adjustable.
The T0 and T4 clock generators may each be in fre-
erun, synchronized, or holdover modes. In freerun,
the clock outputs are simply determined by the accu-
racy of the digitally calibrated OCXO/TCXO. In syn-
chronized mode, the chip phase locks to the selected
input reference. Phase lock may be selected as arbi-
trary or zero phase offset between the reference and
clock outputs. All reference switches are performed
in a hitless manner, and frequency ramp controls
ensure smooth output signal transitions. When
references are switched, the device will minimize
phase transitions in the output clocks. While synchro-
nized, a frequency history is accumulated. In hold-
over mode, the chip outputs are synthesized
according to this or a user supplied history.
The Digital Phase Locked Loop which provides the
critical filtering and frequency/phase control functions
is implemented with Connor-Winfield’s NOVA Kernel
- a set of well-proven algorithms and control that
meet or exceed all requirements and lead the indus-
try in critical jitter and accuracy performance parame-
ters. Filter bandwidth may be user configured.
The device generates 8 independent synchronized
output clocks. The first is at 155.52MHZ. The second
and third clocks may be programmed at 19.44/38.88/
77.76MHZ. The fourth and fifth are at 8kHz and
2kHz. The sixth is programmable at 1, 2, 4, 8, or 16 x
T1 or E1. The seventh is programmable at either
DS3 or E3. The eighth is programmable at either T1
or E1.
Control functions are provided either via a standard
SPI serial bus interface or 8-bit parallel bus register
interfaces. These provide access to the STC4130’s
comprehensive, yet simple to use internal control
and status registers. Parallel bus operation is sup-
ported in the Motorola mode, Intel mode, or Multiplex
bus mode.


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