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M27C1001-35XN3X Folha de dados(PDF) 8 Page - STMicroelectronics |
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M27C1001-35XN3X Folha de dados(HTML) 8 Page - STMicroelectronics |
8 / 17 page M27C1001 8/17 PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed, with a guaranteed margin, in a typical time of 13 seconds. Program- ming with PRESTO II involves in applying a se- quence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During pro- gramming and verify operation, a MARGIN MODE circuit is automatically activated in order to guar- antee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides necessary mar- gin to each programmed cell. Program Inhibit Programming of multiple M27C1001s in parallel with different data is also easily accomplished. Ex- cept for E, all like inputs including G of the parallel M27C1001 may be common. A TTL low level pulse applied to a M27C1001's P input, with E low and VPP at 12.75V, will program that M27C1001. A high level E input inhibits the other M27C1001s from being programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. Figure 6. Programming and Verify Modes AC Waveforms tAVPL VALID AI00714 A0-A16 Q0-Q7 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY Figure 7. Programming Flowchart AI00715C n = 0 Last Addr VERIFY P = 100 µs Pulse ++n = 25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V YES NO YES NO YES NO |
Nº de peça semelhante - M27C1001-35XN3X |
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Descrição semelhante - M27C1001-35XN3X |
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