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TS68332MA20 Folha de dados(PDF) 6 Page - ATMEL Corporation

Nome de Peças TS68332MA20
Descrição Electrónicos  High Highperformance 32-bit Integrated Microcontroller
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Fabricante Electrônico  ATMEL [ATMEL Corporation]
Página de início  http://www.atmel.com
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6
2118A–HIREL–11/05
TS68332
2.1
Signal Description
Figure 2-1 on page 3 illustrates the functional signal groups and Table 2-1 lists the signals and
their function.
Table 2-1.
Signal Index
Signal Name
Mnemonic
Function
Address Bus
A23 - A0
24-bit address bus
Data Bus
D15 - D0
16-bit data bus used to transfer byte or word data per bus cycle
Data Bus Function Codes
FC2 - FC0
Identify the processor state and the address space of the current bus cycle
Boot Chip Select
CSBOOT
Chip-select boot stat up ROM containing user’s reset vector and initialization program
Chip Selects
CS10 - CSO
Enables peripherals at programmed addresses
Bus Request
BR
Indicates that an external device requires bus mastership
Bus Grant
BG
Indicates that current bus cycle is complete and the TS68332 has relinquished the
bus
Bus Grant Acknowledge
BGACK
Indicates that an external device has assumed bus mastership
Data and Size
Acknowledgement
DSACK1,
DSACK0
Provides asynchronous data transfers and dynamic bus sizing
Autovector
AVEC
Requests an automatic vector during an interrupt acknowledge cycle
Read-Modify-Write Cycle
RMC
Identifies the bus cycle as part of an indivisible read-modify-write cycle
Address Strobe
AS
Indicates that a valid address is on the address bus
Data Strobe
DS
During a read cycle, DS indicates that an external device should place valid data on
the data bus. During a write cycle, DS indicates that valid data is on the data bus.
Size
SIZ1 - SIZ0
Indicates the number of bytes remaining to be transferred for this cycle
Read/Write
R/W
Indicates the direction of data transfer on the bus
Interrupt Request Level
IRQ7 - IRQ0
Provides an interrupt priority level to the CPU
Reset
RESET
System reset
Halt
HALT
Suspend external bus activity
Bus Error
BERR
Indicates that an erroneous bus operation is being attempted
System Clockout
CLKOUT
Internal system clock
Crystal Oscillator
EXTAL, XTAL
Connection for an external crystal to the internal oscillator circuit
External Filter Capacitor
XFC
Connection pin for an external capacitor to filter the circuit of the phase-locked loop
Clock Mode Select
MODCK
Selects the source of the internal system clock
Instruction Fetch
IFETCH
Indicates when the CPU is performing an instruction word pre-fetch and when the
instruction pipeline has been flushed
Instruction Pipe
IPIPE
Used to track movement of words through the instruction pipeline
Breakpoint
BKPT
Signals a hardware breakpoint to the CPU
Freeze
FREEZE
Indicates that the CPU has acknowledged a breakpoint
Quotient Out
QUOT
Serial I/O and clock for background debug mode
Test Mode Enable
TSTME
Hardware enable for test mode
Three-State Control
TSC
Places all output drivers in a high-impedance state


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