Os motores de busca de Datasheet de Componentes eletrônicos |
|
HLMP-ED80-XXXXX Folha de dados(PDF) 9 Page - Agilent(Hewlett-Packard) |
|
HLMP-ED80-XXXXX Folha de dados(HTML) 9 Page - Agilent(Hewlett-Packard) |
9 / 51 page 8 Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Units Notes Operating Temperature TA 040 ˚C Power Supply Voltage VDD 4.25 5.0 5.5 volts Register values retained for voltage transients below 4.25 V but greater than 4 V. Power Supply Rise Time VRT 100 ms Supply Noise VN 100 mV Peak to peak within 0-100 MHz. Clock Frequency fCLK 17.4 18.0 18.7 MHz Set by ceramic resonator. Serial Port Clock Frequency SCLK fCLK/4 MHz Resonator Impendance XRES 55 Ω Distance from Lens Reference Z 2.3 2.4 2.5 mm Results in ±0.2 mm DOF. Plane to Surface (See Figure 10.) Speed S 0 14 in/sec @ frame rate = 1500/second. Acceleration A 0.15 g @ frame rate = 1500/second. Light Level onto IC IRRINC 80 25,000 mW/m2 λ = 639 nm 100 30,000 λ = 875 nm SDIO Read Hold Time tHOLD 100 µs Hold time for valid data. (Refer to Figure 28.) SDIO Serial Write-Write Time tSWW 100 µs Time between two write commands. (Refer to Figure 31.) SDIO Serial Write-Read Time tSWR 100 µs Time between write and read operation. (Refer to Figure 32.) SDIO Serial Read-Write Time tSRW 120 ns Time between read and write operation. (Refer to Figure 33.) SDIO Serial Read-Read Time tSRR 120 ns Time between two read commands. (Refer to Figure 33.) Data Delay after PD tCOMPUTE 3.2 ms After tCOMPUTE, all registers contain data from first image after PD . Note that an addi- tional 75 frames for AGC (shutter) stabilization may be required if mouse movement occurred while PD was high. (Refer to Figure 12.) SDIO Write Setup Time tSETUP 60 ns Data valid time before the rising of SCLK. (Refer to Figure 26.) PD Pulse Width tPDW 700 µs Pulse width to initiate the power (to power down the chip) down cycle @ 1500 fps. (Refer to Figure 12 and Figure 14.) PD Pulse Width tPDR 100 µs Pulse width to reset the serial (to reset the serial port) port @ 1500 fps (but may also initiate a power down cycle. Normal PD recovery sequence to be followed. (Refer to Figure 15.) Frame Rate FR 1500 frames/s See Frame_Period register section. Bin Resistor R1 15 K 15 K 37 K Ω Refer to Figure 8. |
Nº de peça semelhante - HLMP-ED80-XXXXX |
|
Descrição semelhante - HLMP-ED80-XXXXX |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |