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RIVA128ZX Folha de dados(PDF) 18 Page - STMicroelectronics

Nome de Peças RIVA128ZX
Descrição Electrónicos  128-BIT 3D MULTIMEDIA ACCELERATOR
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Fabricante Electrônico  STMICROELECTRONICS [STMicroelectronics]
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RIVA128ZX Folha de dados(HTML) 18 Page - STMicroelectronics

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128-BIT 3D MULTIMEDIA ACCELERATOR
RIVA128ZX
18/85
Figure 6.
Single address - no delay by master
Figure 7 shows the RIVA128ZX enqueuing 4 requests, where the first request is delayed by the maximum
2 cycles allowed. START is indicated on clock 2, but the RIVA128ZX does not assert AGPPIPE# until
clock 4. Note that PCIREQ# remains asserted on clock 6 to indicate that the current request is not the last
one. When PCIREQ# is deasserted on clock 7 with AGPPIPE# still asserted this indicates that the current
address is the last one to be enqueued during this transaction. AGPPIPE# must be deasserted on the next
clock when PCIREQ# is sampled as deasserted. If the RIVA128ZX wants to enqueue more requests dur-
ing this bus operation, it continues asserting AGPPIPE# until all of its requests are enqueued or until it has
filled all the available request slots provided by the target.
Figure 7.
Multiple addresses enqueued, maximum delay by RIVA128ZX
2X Data Transfers
2X data transfers are similar to 1X transfers except that an entire 8 bytes are transferred during a single
PCICLK period. This requires that two 4 byte pieces of data are transferred across PCIAD[31:0] for each
CLK period. A read data transfer is described followed by a write transfer.
C1
A1
111
111
xxx
xxx
xxx
xxx
xxx
xxx
PCICLK
AGPPIPE#
PCIAD[31:0]
PCICBE[3:0]#
PCIREQ#
PCIGNT#
AGPST[2:0]
12
3
4
5
6
7
8
A1
111
111
111
xxx
xxx
xxx
xxx
xxx
A2
A3
A4
C1
C2
C3
C4
PCICLK
AGPPIPE#
PCIAD[31:0]
PCICBE#
PCIREQ#
PCIGNT#
AGPST[2:0]
12
3
4
56
7


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