2

Jan, 2008

Document Control #ML0025 Rev 2.0

STK17TA8

Packages

For detailed package size

specifications, see page 26.

NC

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

NC

23

24

INT

NC

NC

NC

NC

48

47

46

45

HSB

NC

NC

W

NC

E

G

48-Pin SSOP

(TOP)

PIN DESCRIPTIONS

Pin Name

I/O

Description

Input

Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array or one of 16 bytes in the clock

register map

I/O

Data: Bi-directional 8-bit data bus for accessing the nvSRAM and RTC

E

Input

Chip Enable: The active low E input selects the device

W

Input

Write Enable: The active low W enables data on the DQ pins to be written to the address location selected on

the falling edge of E

G

Input

Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high

caused the DQ pins to tri-state.

Output

Crystal Connection, drives crystal on startup

Input

Crystal Connection for 32.768 kHz crystal

Power Supply

Power Supply

Power Supply

Power: 3.0V, +20%, -10%

HSB

I/O

Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low external to the

chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected.

(Connection Optional).

INT

Output

Interrupt Control: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor.

Programmable to either active high (push/pull) or active low (open-drain)

Power Supply

Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile stor-

age elements.

Power Supply

Ground

(Blank)

No Connect

Unlabeled pins have no internal connections.