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ST6235BQ6 Folha de dados(PDF) 5 Page - STMicroelectronics |
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ST6235BQ6 Folha de dados(HTML) 5 Page - STMicroelectronics |
5 / 82 page 5/82 ST62T35B/E35B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62T35B and ST62E35B devices are low cost members of the ST62xx 8-bit HCMOS family of microcontrollers, which is targeted at low to me- dium complexity applications. All ST62xx devices are based on a building block approach: a com- mon core is surrounded by a number of on-chip peripherals. The ST62E35B is the erasable EPROM version of the ST62T35B device, which may be used to em- ulate the ST62T35B device, as well as the respec- tive ST6235B ROM devices. Figure 1. Block Diagram TEST NMI INTERRUPT PROGRAM PC STACK LEVEL 1 STACK LEVEL 2 STACK LEVEL 3 STACK LEVEL 4 STACK LEVEL 5 STACK LEVEL 6 POWER SUPPLY OSCILLATOR RESE T DATA ROM USER SELECTABLE DATA RAM PORT A PORT B TIMER DIGITAL 8 BIT CORE TEST/ VPP 8-BIT A/D CONVERTER PA0..PA1 / 20 mA Sink VDDVSS OSCin OSCout RESE T WATCHDO G Memory PORT C SPI (SERIA L PERIPHER AL INTERF ACE) AUTORELOAD TIMER 192 Bytes 79 48 bytes DATA EEPROM 128 Bytes PA2/OVF/ 20 mA Sink PA3/PWM/20 mA Sink PA4/Ain/CP 1 PA5/Ain/CP2 PB0..PB7/Ain PC4..PC7/Ain PORT D PORT E PD0,PD6,PD7/Ain PD1/Ain/Scl PD2/Ain/Si n PD3/Ain/Sout PD4/Ain/R XD1 PD5/Ain/TX D1 PE0...PE7 PA6...PA7/Ain (VPP on EPROM/OTP versions only) TIMER VR01823E UART 4 |
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