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AD5751 Folha de dados(PDF) 10 Page - Analog Devices

Nome de Peças AD5751
Descrição Electrónicos  Industrial I/V Output Driver, Single Supply, 60v Compliance, Programmable Ranges
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
Logo AD - Analog Devices

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Preliminary Technical Data
AD5751
Rev. PrA | Page 10 of 22
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1
CLRSEL 2
CLEAR 3
4
5
SDIN/R0
6
DVCC
7
SDO/VFAULT
8
GND
24
VOUT
23
GND
22
AVDD
21
COMP1
20
COMP2
19
GND
18 IOUT
17
VSENSE+
TOP VIEW
SYNC/RSEL
SCLK/OUTEN
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
LFCSP Pin No.
Mnemonic
Description
1
SDO/VFAULT
In Software Mode, Serial Data Output. Used to clock data from the serial register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the
falling edge of SCLK. Open Drain Output, must be connected to a pull up resistor.
In Hardware mode, acts as a SHORT circuit Fault alert pin. This pin is asserted low when
an SHORT circuit. Error is detected. Open drain output, must be connected to a pull-up
resistor.
2
CLRSEL
In Hardware or software mode, selects the clear value, either zero-scale or mid-scale
code. In Software mode, this pin is implemented as a logic OR with the internal CLRSEL
bit.
3
CLEAR
Active High Input. Asserting this pin sets the Output Current/Voltage to zero-scale code
or mid-scale code of range selected (user-selectable). CLEAR is a LOGIC OR with the
internal CLEAR bit.
4
DVCC
Digital Power Supply
5
GND
Ground Connection.
6
SYNC/RSEL
In Software Mode, Positive edge sensitive latch, a rising edge will parallel load the input
shift register data into the INPUT register, also updating the output.
In Hardware mode, this pin chooses whether internal/external current sense resistor is
used
7
SCLK/OUTEN
In Software Mode, Serial Clock Input. Data is clocked into the shift register on the falling
edge of SCLK. This operates at clock speeds up to 30 MHz.
In Hardware mode, this pin acts as an output enable pin.
8
SDIN/RO
In Software Mode, Serial Data Input. Data must be valid on the falling edge of SCLK.
In Hardware Mode, R0 is Range Decode Bit. This pin, in conjunction with R2, R3, R1
choose the output current/voltage range setting on the part.
9
AD2/R1
In Software Mode, AD2 is Device Addressing bit. This pin, in conjunction with AD1, AD0
allow up to 8 devices to be addressed on one bus.
In Hardware Mode, R1 is Range Decode Bit. This pin, in conjunction with R2, R3, R0
choose the output current/voltage range setting on the part.
10
AD1/R2
In Software Mode, AD1 is Device Addressing bit. This pin, in conjunction with AD2, AD0
allow up to 8 devices to be addressed on one bus.


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