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ADXL180 Folha de dados(PDF) 6 Page - Analog Devices |
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ADXL180 Folha de dados(HTML) 6 Page - Analog Devices |
6 / 56 page ADXL180 Rev. 0 | Page 6 of 56 Parameter1 Symbol Min Typ Max Unit Test Conditions/Comments ASYNCHRONOUS MODE TIMING2 Message Transmission Period Phase 2, Mode 0 tPM0 456 μs ADIFX compatible All Other Phases and Modes tP 228 μs Initialization State (Phase 1) tI 100 ms Device Data State (Phase 2) ms Mode 0 tDD0 4.10 ms Mode 1 tDD1 109 ms Mode 2 tDD2 109 ms Mode 3 tDD3 117 ms Self-Test State (Phase 3) Self-Test Time3 tST 394 ms See Figure 26 Self-Test Interval tSTI 21.9 ms See Figure 26 Self-Test Cycle tSTC 65.7 ms See Figure 26 Auto-Zero Initialization State (Phase 4) tAZ 14.94 sec SYNCHRONOUS MODE TIMING4 Message Transmission Period tPS N/A Determined by sync pulse, See Figure 12, minimum tPS = tSPD + tSTD + tM + tB Initialization State1 (Phase 1) tI 100 ms Device Data State (Phase 2) ms Mode 0 tDD0s 9 × tPS ms Mode 1 tDD1s 480 × tPS ms Mode 2 tDD2s 480 × tPS ms Mode 3 tDD3s 512 × tPS ms Self-Test State (Phase 3) Self-Test Time3 tSTS 1728 × tPS ms Self-Test Interval tSTIS 96 × tPS ms Self-Test Cycle tSTCS 288 × tPS ms Auto-Zero Initialization State (Phase 4) tAZs 65,535 × tPS sec CLOCK Period2 tCLK 1.05 1.0 0.95 μs fCLK = 1/tCLK PSRR5 <1 LSB 8-bit LSB; test conditions: VBP − VBN = 7.00 V, VAC = 500 mV p-p, 100 kHz to 1.1 MHz POWER SUPPLY HOLDUP TIME 500 ns @ IBUS = ISIG THERMAL RESISTANCE, JUNCTION TO CASE θJC 30 °C/W 1 All parameters are specified using the application circuit shown in Figure 6. CB = 10 nF, CVDD = 100 nF. 2 All timing is driven from the on-chip master clock. 3 tST and tSTS are the times for six self-test cycles. This is the maximum number of cycles in the internal self-test mode. 4 Transmission timing is defined by the internal system clock in asynchronous mode and by the synchronization pulse period in synchronous mode. |
Nº de peça semelhante - ADXL180 |
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Descrição semelhante - ADXL180 |
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