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FAN3121TMPX Folha de dados(PDF) 6 Page - Fairchild Semiconductor |
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FAN3121TMPX Folha de dados(HTML) 6 Page - Fairchild Semiconductor |
6 / 21 page © 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3121 / FAN3122 • Rev. 1.0.0 6 Electrical Characteristics Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit Supply VDD Operating Range 4.5 18.0 V TTL 0.65 0.90 IDD Supply Current, Inputs / EN Not Connected CMOS (8) 0.58 0.85 mA VON Turn-On Voltage 3.5 4.0 4.3 V VOFF Turn-Off Voltage 3.30 3.75 4.10 V Inputs (FAN312xT) (9) VIL_T INx Logic Low Threshold 0.8 1.0 V VIH_T INx Logic High Threshold 1.7 2.0 V IIN+ Non-Inverting Input Current IN from 0 to VDD -1 175 µA IIN- Inverting Input Current IN from 0 to VDD -175 1 µA VHYS_T TTL Logic Hysteresis Voltage 0.40 0.70 0.85 V Inputs (FAN312xC) (9) VIL_C INx Logic Low Threshold 30 38 %VDD VIH_C INx Logic High Threshold 55 70 %VDD IIN+ Non-Inverting Input Current IN from 0 to VDD -1 175 µA IIN- Inverting Input Current IN from 0 to VDD -175 1 µA VHYS_C CMOS Logic Hysteresis Voltage 12 17 24 %VDD ENABLE (FAN3121, FAN3122) VENL Enable Logic Low Threshold EN from 5V to 0V 1.2 1.6 2.0 V VENH Enable Logic High Threshold EN from 0V to 5V 1.8 2.2 2.6 V VHYS_T TTL Logic Hysteresis Voltage 0.2 0.6 0.8 V RPU Enable Pull-up Resistance 68 100 134 kΩ tD1, tD2 Propagation Delay, EN Rising (10) 8 17 27 ns tD1, tD2 Propagation Delay, EN Falling (10) 14 21 33 ns Output ISINK OUT Current, Mid-Voltage, Sinking (11) OUT at VDD/2, CLOAD=1.0µF, f=1kHz 9.7 A ISOURCE OUT Current, Mid-Voltage, Sourcing (11) OUT at VDD/2, CLOAD=1.0µF, f=1kHz 7.1 A IPK_SINK OUT Current, Peak, Sinking (11) CLOAD=1.0µF, f=1kHz 11.4 A IPK_SOURCE OUT Current, Peak, Sourcing (11) CLOAD=1.0µF, f=1kHz 10.6 A tRISE Output Rise Time (10) CLOAD=10nF 18 23 29 ns tFALL Output Fall Time (10) CLOAD=10nF 11 19 27 ns tD1, tD2 Output Propagation Delay, CMOS Inputs (10) 0 – 12VIN, 1V/ns Slew Rate 9 18 28 ns tD1, tD2 Output Propagation Delay, TTL Inputs (10) 0 – 5VIN, 1V/ns Slew Rate 9 23 35 ns IRVS Output Reverse Current Withstand (11) 1500 mA Notes: 8. Lower supply current due to inactive TTL circuitry. 9. EN inputs have modified TTL thresholds; refer to the ENABLE section. 10. See Timing Diagrams of Figure 8 and Figure 9. 11. Not tested in production. |
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