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STPC12HDYC Folha de dados(PDF) 2 Page - STMicroelectronics |
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STPC12HDYC Folha de dados(HTML) 2 Page - STMicroelectronics |
2 / 111 page STPC ® ATLAS 2/111 Issue 1.0 - July 24, 2002 DESCRIPTION The STPC Atlas integrates a standard 5th generation x86 core along with a powerful UMA graphics/video chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with standard I/O interfaces to provide a single PC compatible subsystem on a single device, suitable for all kinds of terminal and industrial appliances. s X86 Processor core s Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. s Can access up to 4GB of external memory. s 8Kbyte unified instruction and data cache with write back and write through capability. s Parallel processing integral floating point unit, with automatic power down. s Runs up to 133 MHz (X2). s Fully static design for dynamic clock control. s Low power and system management modes. s Optimized design for 2.5V operation. s SDRAM Controller s 64-bit data bus. s Up to 90MHz SDRAM clock speed. s Integrated system memory, graphic frame memory and video frame memory. s Supports 8MB up to 128 MB system memory. s Supports 16-Mbit, 64-Mbit and 128-Mbit SDRAMs. s Supports 8, 16, 32, 64, and 128 MB DIMMs. s Supports buffered, non buffered, and registered DIMMs s 4-line write buffers for CPU to DRAM and PCI to DRAM cycles. s 4-line read prefetch buffers for PCI masters. s Programmable latency s Programmable timing for SDRAM parameters. s Supports -8, -10, -12, -13, -15 memory parts s Supports memory hole between 1MB and 8MB for PCI/ISA busses. s 32-bit access, Autoprecharge & Power-down are not supported. s Enhanced 2D Graphics Controller s Supports pixel depths of 8, 16, 24 and 32 bit. s Full BitBLT implementation for all 256 raster operations defined for Windows. s Supports 4 transparent BLT modes - Bitmap Transparency, Pattern Transparency, Source Transparency and Destination Transparency. s Hardware clipping s Fast line draw engine with anti-aliasing. s Supports 4-bit alpha blended font for anti- aliased text display. s Complete double buffered registers for pipelined operation. s 64-bit wide pipelined architecture running at 90 MHz. Hardware clipping s CRT Controller s Integrated 135MHz triple RAMDAC allowing for 1280 x 1024 x 75Hz display. s 8-, 16-, 24-bit pixels. s Interlaced or non-interlaced output. s Video Input port s Accepts video inputs in CCIR 601/656 mode. s Optional 2:1 decimator s Stores captured video in off setting area of the onboard frame buffer. s HSYNC and B/T generation or lock onto external video timing source. s Video Pipeline s Two-tap interpolative horizontal filter. s Two-tap interpolative vertical filter. s Color space conversion (RGB to YUV and YUV to RGB). s Programmable window size. s Chroma and color keying for integrated video overlay. |
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Descrição semelhante - STPC12HDYC |
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