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FAN5099MTCX Folha de dados(PDF) 3 Page - Fairchild Semiconductor |
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FAN5099MTCX Folha de dados(HTML) 3 Page - Fairchild Semiconductor |
3 / 24 page © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN5099 Rev. 1.1.5 3 Pin Configuration Figure 2. Pin Assignment Pin Description Pin No. Pin Name Pin Description 1FBLDO LDO Feedback. This node is regulated to VREF. 2R(T) Oscillator Set Resistor. This pin provides oscillator switching frequency adjustment. By plac- ing a resistor (RT) from this pin to GND, the nominal 50kHz switching frequency is increased. 3ILIM Current Limit. A resistor from this pin to GND sets the current limit. 4 SS Soft-Start. A capacitor from this pin to GND programs the slew rate of the converter and the LDO during initialization. It also sets the time by which the converter delays when restarting after a fault occurs. SS has to reach 1.2V before fault shutdown feature is enabled. The LDO is enabled when SS reaches 2.2V. 5COMP COMP. The output of the error amplifier drives this pin. 6FB Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combi- nation with the COMP pin, to compensate the feedback loop of the converter. 7EN Enable. Enables operation when pulled to logic high. Toggling EN resets the regulator after a latched fault condition. This is a CMOS input whose state is indeterminate if left open and needs to be properly biased at all times. 8AGND Analog Ground. The signal ground for the IC. All internal control voltages are referred to this pin. Tie this pin to the ground island/plane through the lowest impedance connection available. 9SW Switching Node. Return for the high-side MOSFET driver and a current sense input. Connect to source of high-side MOSFET and drain of low-side MOSFET. 10 HDRV High-Side Gate Drive Output. Connect to the gate of the high-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the high-side MOSFET is turned off. 11 BOOT Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor as shown in Figure 1. 12 PGND Power Ground. The return for the low-side MOSFET driver. Connect to source of low-side MOSFET. 13 LDRV Low-Side Gate Drive Output. Connect to the gate of the low-side power MOSFETs. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET is turned off. 14 R(RAMP) Ramp Resistor. A resistor from this pin to VIN sets the ramp amplitude and provides voltage feed-forward. 15 VCC VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. This pin has a shunt regulator which draws current when the input voltage is above 5.6V. 16 GLDO Gate Drive for the LDO. Turned off (low) until SS is greater than 2.2V. |
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Descrição semelhante - FAN5099MTCX |
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