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LC07422T Folha de dados(PDF) 7 Page - Sanyo Semicon Device

Nome de Peças LC07422T
Descrição Electrónicos  CMOS IC Audio CODEC with Video Driver
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Fabricante Electrônico  SANYO [Sanyo Semicon Device]
Página de início  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC07422T Folha de dados(HTML) 7 Page - Sanyo Semicon Device

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LC07422T
No.A0908-7/10
Outline of operation
1. System reset/power-down
When the RESET_X pin is set to “VSS,” the system is reset, and all the circuits go into the power-down mode. After
the power is turned on, perform this operation once without fail.
When the system is reset, the contents of the register are initialized. (See register tables.)
For the subsequent startup of each function, refer to the section “Control/start/stop sequence for reducing pop noise.”
2. ALC
When the ALC is active, the PGA (programmable gain amplifier) gain value is automatically adjusted so that the
audio level becomes the preset value. The PGA gain can be adjusted in a range from +34 to -14dB.
By limiting the gain adjustment range to 0 to -14dB, this adjustment function can be made to work as a limiter
function.
The ALC operation can be stopped by a register setting. The ALC is then placed in the manual mode, and the PGA
gain is adjusted by the register setting. For details, refer to the section “Description of ALC/limiter operation.”
3. A/D converter
The A/D converter converts the analog PGA output signals into digital data, and the digital data is then output as 16-
bit serial audio data.
There are three formats supported: I
2S, left justification and right justification.
The A/D converter incorporates a high-pass filter for canceling DC offset.
The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V.
4. D/A converter
The D/A converter converts the digital 16-bit serial audio data into analog signals.
There are three formats supported: I
2S, left justification and right justification.
The D/A converter incorporates a high-pass filter for canceling DC offset.
The analog input range of the ADC is 0.6VDDadc. When VDDadc is 2.8V, 0dBfs is 1.68V.
5. EVR
This is an analog EVR. The gain can be set within a range from 0 dB to -65dB or mute (adjustable in steps). It is
incorporated in the headphone and speaker amplifier path so that the output level of the headphones and speaker can
be controlled separately from the line-out output.
6. Selector
This selector is for selecting either the DAC or PGA output of the ALC. When the DAC output has been selected, the
DAC output signals are output as the speaker amplifier and headphone amplifier output signals. When the PGA
output has been selected, the signals from line input are all turned into analog signals to become the speaker
amplifier and headphone amplifier output signals.
7. MIX
This is the mixing circuit for the left- and right-channel audio signals. In other words, this functions as a monaural
signal generator circuit to provide a monaural speaker amplifier input. The left- and right-channel signals are mixed
on a 1:1 basis and then output through the -2dB amplifier.
If the left- and right-channel signals are identical, the total gain becomes 4dB (= 6dB(doubled) -2dB).
8. SP AMP
This is the monaural speaker amplifier. Its maximum output is 250mW (typ VDD =2.8V, 8Ω, THD+N = 10%).
Inputs to the amplifier are the audio signal SP_AMPin pin and BEEPin pin signals.
For the BEEPin pin signal, the mixing can be set ON or OFF, and the gain level can be selected (from –21 to –12dB).
A thermal shutdown function is provided. When it is left enabled, the speaker amplifier operation is automatically
shut down when the chip temperature has reached a high level.


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