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74LVT273DB Folha de dados(PDF) 4 Page - NXP Semiconductors |
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74LVT273DB Folha de dados(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74LVT273_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 10 September 2008 4 of 17 NXP Semiconductors 74LVT273 3.3 V octal D-type flip-flop 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration for SO20 and (T)SSOP20 Fig 5. Pin configuration for DHVQFN20 74LVT273 MR VCC Q0 Q7 D0 D7 D1 D6 Q1 Q6 Q2 Q5 D2 D5 D3 D4 Q3 Q4 GND CP 001aai737 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aai738 74LVT273 Transparent top view GND(1) Q4 D3 Q3 D4 D2 D5 Q2 Q5 Q1 Q6 D1 D6 D0 D7 Q0 Q7 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description MR 1 master reset input (active LOW) Q0 to Q7 2, 5, 6, 9, 12, 15, 16, 19 data output D0 to D7 3, 4, 7, 8, 13, 14, 17, 18 data input GND 10 ground (0 V) CP 11 clock pulse input (active on rising edge) VCC 20 positive supply voltage |
Nº de peça semelhante - 74LVT273DB |
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Descrição semelhante - 74LVT273DB |
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