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ADC0808S250 Folha de dados(PDF) 4 Page - NXP Semiconductors |
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ADC0808S250 Folha de dados(HTML) 4 Page - NXP Semiconductors |
4 / 23 page ADC0808S125_ADC0808S250_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 7 October 2008 4 of 23 NXP Semiconductors ADC0808S125/250 Single 8-bit ADC, up to 125 MHz or 250 MHz [1] See Table 3. i.c. 15 - internally connected; leave open OGND3 16 G data output ground 3 CCS 17 O complete conversion signal output i.c. 18 - internally connected; leave open CE_N 19 I(CMOS) chip enable input (active LOW) IR 20 O(CMOS) in-range output OTC 21 I(CMOS) control input for 2’s complement output DGND1 22 G digital ground 1 VCCD1(1V8) 23 P digital supply voltage 1 (1.8 V) n.c. 24 - not connected n.c. 25 - not connected CCSSEL 26 I(CMOS) control input for CCS frequency selection NC1V8 27 I not connected or connected to VCCD1(1V8) AGND1 28 G analog ground 1 CMADC 29 O regulator common-mode ADC output FSIN/REFSEL 30 I full-scale reference voltage input/internal or external reference selection AGND2 31 G analog ground 2 INN 32 I complementary analog input IN 33 I analog input VCCA1(3V3) 34 P analog supply voltage 1 (3.3 V) i.c. 35 - internally connected; leave open CLKSEL 36 I(CMOS) control input for clock input selection CLK+ 37 I clock input CLK − 38 I complementary clock input DEL0 39 I(CMOS) complete conversion signal delay input 0 DEL1 40 I(CMOS) complete conversion signal delay input 1 D0 41 O data output bit 0 i.c. 42 - internally connected; leave open VCCO4(1V8) 43 P data output supply voltage 4 (1.8 V) D1 44 O data output bit 1 i.c. 45 - internally connected; leave open OGND4 46 G data output ground 4 D2 47 O data output bit 2 i.c. 48 - internally connected; leave open DGND - G digital ground; exposed die pad Table 2. Pin description …continued Symbol Pin Type[1] Description |
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