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ISL54220IUZ-T Folha de dados(PDF) 2 Page - Intersil Corporation |
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ISL54220IUZ-T Folha de dados(HTML) 2 Page - Intersil Corporation |
2 / 15 page 2 FN6819.1 February 4, 2010 Pin Configurations ISL54220 (10 LD 3.0X3.0 TDFN) TOP VIEW ISL54220 (10 LD MSOP) TOP VIEW ISL54220 (10 LD 1.8X1.4 µTQFN) TOP VIEW NOTE: 1. Switches Shown for SEL = Logic “1” and OE = Logic “0”. SEL HSD1+ D+ HSD2+ HSD1- GND 1 2 3 4 5 10 9 8 7 6 D- HSD2- VDD OE LOGIC CONTROL PD SEL HSD1+ D+ HSD2+ HSD1- GND 1 2 3 4 5 10 9 8 7 6 D- HSD2- VDD OE LOGIC CONTROL 8 10 D- OE D+ VDD 9 7 2 3 4 GND HSD1+ HSD2+ 5 SEL 1 6 HSD1- HSD2- Truth Table OE SEL HSD1-, HSD1+ HSD2-, HSD2+ 0 0 ON OFF 01 OFF ON 1X OFF OFF Logic “0” when ≤ 0.5V, Logic “1” when ≥ 1.4V with a 2.7V to 3.6V Supply. Pin Descriptions TDFN MSOP µTQFN NAME FUNCTION 10 10 9 VDD Power Supply (2.7V to 5.5V) 1 1 10 SEL Select Logic Control Input 2 2 1 HSD1+ USB Data Port (Channel 1 Positive Input) 3 3 2 HSD2+ USB Data Port (Channel 2 Positive Input) 4 4 3 D+ USB Data Common Positive Port 5 5 4 GND Ground Connection 6 6 5 D- USB Data Common Negative Port 7 7 6 HSD2- USB Data Port (Channel 2 Negative Input) 8 8 7 HSD1- USB Data Port (Channel 1 Negative Input) 99 8 OE Bus Switch Enable PD - - PD Thermal Pad. Tie to Ground or Float ISL54220 |
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