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ACEX1K Folha de dados(PDF) 6 Page - Altera Corporation |
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ACEX1K Folha de dados(HTML) 6 Page - Altera Corporation |
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6 / 86 page  6 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet f For more information on the configuration of ACEX 1K devices, see the following documents: ■ Configuration Devices for ACEX, APEX, FLEX, & Mercury Devices Data Sheet ■ MasterBlaster Serial/USB Communications Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ACEX 1K devices are supported by Altera development systems, which are integrated packages that offer schematic, text (including AHDL), and waveform design entry, compilation and logic synthesis, full simulation and worst-case timing analysis, and device configuration. The software provides EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The Altera software works easily with common gate array EDA tools for synthesis and simulation. For example, the Altera software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the Altera software contains EDA libraries that use device- specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the Altera development system includes DesignWare functions that are optimized for the ACEX 1K device architecture. The Altera development systems run on Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations. f For more information, see the MAX+PLUS II Programmable Logic Development System & Software Data Sheet and the Quartus Programmable Logic Development System & Software Data Sheet. Functional Description Each ACEX 1K device contains an enhanced embedded array that implements memory and specialized logic functions, and a logic array that implements general logic. The embedded array consists of a series of EABs. When implementing memory functions, each EAB provides 4,096 bits, which can be used to create RAM, ROM, dual-port RAM, or first-in first-out (FIFO) functions. When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions. |
Nº de peça semelhante - ACEX1K_03 |
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Descrição semelhante - ACEX1K_03 |
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