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CDCE18005RGZR Folha de dados(PDF) 5 Page - Texas Instruments |
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CDCE18005RGZR Folha de dados(HTML) 5 Page - Texas Instruments |
5 / 58 page Interface and Control Block Interface & Control /Power_Down /SYNC EEPROM(DefaultConfiguration) Device Hardware SPI_LE SPI_CLK SPI_MISO SPI_MOSI Register0 StaticRAM(DeviceRegisters) Register1 Register2 Register3 Register4 Register5 Register6 Register7 Register8 Register0 Register1 Register2 Register3 Register4 Register5 Register6 Register7 CDCE18005 www.ti.com........................................................................................................................................................................................... SCAS863 – NOVEMBER 2008 The CDCE18005 is a highly flexible and configurable architecture and as such contains a number of registers so that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM determine device configuration at all times. The CDCE18005 implements the SPI Interface Mode. SPI Interface Mode is used to access the device RAM and EEPROM either during normal operation (if the host system provides a native SPI interface) or during device configuration (i.e. device programming). During power up the EEPROM content gets copied into the registers after the detection of a valid device power-up. The EEPROM can be locked enabling the designer to implement a fault tolerant design. Figure 4. CDCE18005 Interface and Control Block Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s) :CDCE18005 |
Nº de peça semelhante - CDCE18005RGZR |
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Descrição semelhante - CDCE18005RGZR |
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