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CDCE62005RGZR Folha de dados(PDF) 3 Page - Texas Instruments |
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CDCE62005RGZR Folha de dados(HTML) 3 Page - Texas Instruments |
3 / 76 page PACKAGE 37 1 24 48 25 36 T To op p V Viie ew w 12 13 Not up to Scale CDCE62005 www.ti.com........................................................................................................................................................................................... SCAS862 – NOVEMBER 2008 The CDCE62005 is packaged in a 48-Pin Plastic Quad Flatpack Package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments Package Designator is: RGZ (S-PQFP-N48) Figure 2. 48-Pin QFN Package Outline PIN FUNCTIONS PIN TYPE DESCRIPTION NAME QFN VCC_OUT 8, 11, Power 3.3V Supply for the Output Buffers 18, 21, 26, 29, 32 VCC_AUXOUT 15 Power 3.3V to Power the AUX_OUT circuitry VCC1_PLL 5 A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required) VCC2_PLL 39, 42 A. Power 3.3V PLL Supply Voltage for the PLL circuitry. (Filter Required) VCC_VCO 34, 35 A. Power 3.3V VCO Input Buffer and Circuitry Supply Voltage. (Filter Required) VCC_IN_PRI 47 A. Power 3.3V References Input Buffer and Circuitry Supply Voltage. VCC_IN_SEC 1 A. Power 3.3V References Input Buffer and Circuitry Supply Voltage. VCC_AUXIN 44 A. Power 3.3V Crystal Oscillator Input Circuitry. GND_VCO 36 Ground Ground that connects to VCO Ground. (VCO_GND is shorted to GND) GND PAD Ground Ground is on Thermal PAD. See Layout recommendation SPI_MISO 22 OD In SPI Mode it is an Open Drain Output and it functions as a Master In Slave Out as a serial Control Data Output to CDCE62005 . SPI_LE 25 I LVCMOS input, control Latch Enable for Serial Programmable Interface (SPI), with Hysteresis in SPI Mode. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level “1”. SPI_CLK 24 I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level “1”. SPI_MOSI 23 I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62005 for the SPI bus interface. The input has an internal 150-k Ω pull-up resistor if left unconnected it will default to logic level “1”. TEST_MODE 33 I This pin should be tied high or left unconnected. Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s) :CDCE62005 |
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