1

Data sheet acquired from Harris Semiconductor

SCHS139

Features

• Hysteresis on Clock Inputs for Improved Noise Immu-

nity and Increased Input Rise and Fall Times

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

• Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

Description

The Harris CD74HC107 and CD74HCT107 utilize silicon

gate CMOS technology to achieve operating speeds

equivalent to LSTTL parts. They exhibit the low power

consumption of standard CMOS integrated circuits, together

with the ability to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock

inputs and Q and Q outputs. They change state on the

negative-going transition of the clock pulse. Reset is

accomplished asynchronously by a low level input.

This device is functionally identical to the HC/HCT73 but

differs in terminal assignment and in some parametric limits.

The 74HCT logic family is functionally as well as pin

compatible with the standard 74LS family.

Pinout

CD74HC107, CD74HCT107

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

PACKAGE

PKG.

NO.

CD74HC107E

-55 to 125

14 Ld PDIP

E14.3

CD74HCT107E

-55 to 125

14 Ld PDIP

E14.3

CD74HC107M

-55 to 125

14 Ld SOIC

M14.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical

specifications. Please contact your local sales office or Harris

customer service for ordering information.

1J

1Q

1Q

1K

2Q

2Q

GND

1R

1CP

2K

2R

2CP

2J

1

2

3

4

5

6

7

14

13

12

11

10

9

8

March 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

Copyright

File Number

1722.1

CD74HC107,

CD74HCT107

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

[ /Title

(CD74

HC107

,

CD74

HCT10

7)

/Sub-

ject

(Dual

J-K

Flip-

Flop

with

Reset

Nega-

tive-